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Arithmetic and Logical Instructions

In all instructions below Src2 can either be a register or an immediate value (a 16 bit integer). The immediate forms of the instructions are only included for reference. The assembler will translate the more general form of an instruction (e.g. add) into the immediate form (e.g. addi) if the second argument is constant.


abs Rdest RsrcAbsolute Value ${}^{\dagger}$
Put the absolute value of the integer from register Rsrc in register Rdest.


add Rdest Rsrc1 Src2Addition (with overflow)
addi Rdest Rsrc1 ImmAddition Immediate (with overflow)
addu Rdest Rsrc1 Src2Addition (without overflow)
addiu Rdest Rsrc1 ImmAddition Immediate (without overflow)
Put the sum of the integers from register Rsrc1 and Src2 (or Imm) into register Rdest.


and Rdest Rsrc1 Src2AND
andi Rdest Rsrc1 ImmAND Immediate
Put the logical AND of the integers from register Rsrc1 and Src2 (or Imm) into register Rdest.


div Rsrc1 Rsrc2Divide (signed)
divu Rsrc1 Rsrc2Divide (unsigned)
Divide the contents of the two registers. divu treats is operands as unsigned values. Leave the quotient in register lo and the remainder in register hi. Note that if an operand is negative the remainder is unspecified by the MIPS architecture and depends on the conventions of the machine on which SPIM is run.


div Rdest Rsrc1 Src2Divide (signed with overflow) ${}^{\dagger}$
divu Rdest Rsrc1 Src2Divide (unsigned without overflow) ${}^{\dagger}$
Put the quotient of the integers from register Rsrc1 and Src2 into register Rdest. divu treats is operands as unsigned values.


mul Rdest Rsrc1 Src2Multiply (without overflow) ${}^{\dagger}$


mulo Rdest Rsrc1 Src2Multiply (with overflow) ${}^{\dagger}$
mulou Rdest Rsrc1 Src2Unsigned Multiply (with overflow) ${}^{\dagger}$
Put the product of the integers from register Rsrc1 and Src2 into register Rdest.


mult Rsrc1 Rsrc2Multiply
multu Rsrc1 Rsrc2Unsigned Multiply
Multiply the contents of the two registers. Leave the low-order word of the product in register lo and the high-word in register hi.


neg Rdest RsrcNegate Value (with overflow) ${}^{\dagger}$
negu Rdest RsrcNegate Value (without overflow) ${}^{\dagger}$
Put the negative of the integer from register Rsrc into register Rdest.


nor Rdest Rsrc1 Src2NOR
Put the logical NOR of the integers from register Rsrc1 and Src2 into register Rdest.


not Rdest RsrcNOT ${}^{\dagger}$
Put the bitwise logical negation of the integer from register Rsrc into register Rdest.


or Rdest Rsrc1 Src2OR
ori Rdest Rsrc1 ImmOR Immediate
Put the logical OR of the integers from register Rsrc1 and Src2 (or Imm) into register Rdest.


rem Rdest Rsrc1 Src2Remainder ${}^{\dagger}$
remu Rdest Rsrc1 Src2Unsigned Remainder ${}^{\dagger}$
Put the remainder from dividing the integer in register Rsrc1 by the integer in Src2 into register Rdest. Note that if an operand is negative the remainder is unspecified by the MIPS architecture and depends on the conventions of the machine on which SPIM is run.


rol Rdest Rsrc1 Src2Rotate Left ${}^{\dagger}$
ror Rdest Rsrc1 Src2Rotate Right ${}^{\dagger}$
Rotate the contents of register Rsrc1 left (right) by the distance indicated by Src2 and put the result in register Rdest.


sll Rdest Rsrc1 Src2Shift Left Logical
sllv Rdest Rsrc1 Rsrc2Shift Left Logical Variable
sra Rdest Rsrc1 Src2Shift Right Arithmetic
srav Rdest Rsrc1 Rsrc2Shift Right Arithmetic Variable
srl Rdest Rsrc1 Src2Shift Right Logical
srlv Rdest Rsrc1 Rsrc2Shift Right Logical Variable
Shift the contents of register Rsrc1 left (right) by the distance indicated by Src2 (Rsrc2) and put the result in register Rdest.


sub Rdest Rsrc1 Src2Subtract (with overflow)
subu Rdest Rsrc1 Src2Subtract (without overflow)
Put the difference of the integers from register Rsrc1 and Src2 into register Rdest.


xor Rdest Rsrc1 Src2XOR
xori Rdest Rsrc1 ImmXOR Immediate
Put the logical XOR of the integers from register Rsrc1 and Src2 (or Imm) into register Rdest.


next up previous
Next: Constant-Manipulating Instructions Up: Description of the MIPS Previous: Addressing Modes
Ian Moor
1998-09-11