Ports List, part 2 of 3 Copyright (c) 1989-1999,2000 Ralf Brown ----------P0140014F-------------------------- PORT 0140-014F - SCSI (alternate Small Computer System Interface) adapter Note: first adapter is at 0340-034F ----------P0140014F-------------------------- PORT 0140-014F - Xirlink/Relialogic XL-220/221 SCSI adapter Range: alternate address at 0150, 0160, 0170 Notes: XL-220/221 are based on LOGIC Devices L53C80JC4 SCSI controller which is compatible with Symbios Logic (formaerly NCR) 53C80 each SCSI data pin is inverted and compared with correcponding bit in the ID select register; if any matches are found while a bus free condition exists and SEL is active, SCSI controller will genarate an interrupt to indicate a selection or reselection pseudo-DMA register is provided by some on-card PLM, and decodes any address in the range 01x8-01xF; it should be accessed with 16-bit I/O instructions only causing 2 SCSI REQ/ACK hanshakes (8-bit I/O is treated as 16-bit, and second byte is lost); delayed assertion of the REQ signal or bus free condition on the SCSI bus causes the pseudo-DMA register to prolong ISA I/O cycle not asserting IOCHRDY signal (SCSI phase mismatch doesn't), and so may cause ISA bus to hang in not ready state! SCSI BIOS is an 8K ROM located at C8000-CBFFF if I/O port range 0140-014F is selected, at CC000-CFFFF if I/O port range 0150-015F is selected, at D8000-DBFFF if I/O port range 0160-016F is selected, and at DC000-DFFFF if I/O port range 0170-017F is selected 0140 R- current SCSI data bus register 0140 -W output data register 0141 RW initiator command register (see #P0496) 0142 RW mode register (see #P0497) 0143 RW target command register (see #P0498) 0144 R- current SCSI control register (see #P0499) 0144 -W ID select register 0145 R- DMA status register (see #P0500) 0145 -W start DMA send register any write starts DMA send 0146 R- input data register temporarily holds data byte received from the SCSI bus in DMA mode 0146 -W start DMA target receive register any write starts target mode DMA receive 0147 R- reset error/interrupt register any read resets the interrupt request latch and the error latches 0147 -W start DMA initiator mode receive register any write starts initiator mode DMA receive 0148w RW pseudo-DMA register Bitfields for initiator command register: Bit(s) Description (Table P0496) 7 assert RST 6 (read) arbitration in progress (write) test mode 5 (read) lost arbitration 4 assert ACK 3 assert BSY 2 assert SEL 1 assert ATN 0 assert data bus SeeAlso: #P0497,#P0498,#P0499,#P0500 Bitfields for mode register: Bit(s) Description (Table P0497) 7 block mode 6 target mode 5 enable parity check 4 enable parity interrupt 3 enable end of DMA interrupt 2 monitor BSY 1 DMA mode 0 arbitrate SeeAlso: #P0496 Bitfields for target command register: Bit(s) Description (Table P0498) 7 (read) last byte sent 6-4 reserved 3 assert REQ 2 assert MSG 1 assert C/D 0 assert I/O SeeAlso: #P0496 Bitfields for current SCSI control register: Bit(s) Description (Table P0499) 7 RST 6 BSY 5 REQ 4 MSG 3 C/D 2 I/O 1 SEL 0 parity SeeAlso: #P0496 Bitfields for DMA status register: Bit(s) Description (Table P0500) 7 end of DMA 6 DMA request 5 parity error 4 interrupt request 3 phase match 2 BSY error 1 ATN 0 ACK SeeAlso: #P0496 ----------P0140014F-------------------------- PORT 0140-014F - Future Domain TMC-16x0 SCSI adapter Range: alternate address at 0150, 0160, 0170 Notes: TMC-1650/1670 have a 25-pin external connector, whereas the 1660 and 1680 have a SCSI-2 50-pin high-density external connector TMC-1670/1680 have floppy disk controller built in BIOS versions prior to 3.2 assigned SCSI ID 6 to SCSI adapter, versions 3.2 and greater use SCSI ID 7 the drive ordering implemented in BIOS versions 3.4 and 3.5 is the opposite of the order (currently) used by the rest of the SCSI industry--for example, under DOS SCSI ID 0 will be D: and SCSI ID 1 will be C: Future Domain TMC-16x0 SCSI adapter series are based upon Future Domain TMC-1800/18C50/18C30 SCSI controllers TMC-1800/18C50/18C30 are ISA SCSI controllers, TMC-36C70 is a PCI version of TMC-18C30 TMC-1800/18C50 have 8K FIFO, TMC-18C30/36C70 have 2K FIFO Future Domain TMC-1650/1660/1670/1680/1610M/1610MER/1610MEX SCSI adapters are based on TMC-1800/18C50/18C30 Quantum ISA-200S/250MG SCSI adapters are based on TMC-18C50 (?) Future Domain TMC-3260 and Adaptec AHA-2920 PCI SCSI adapters are based on TMC-36C70 0140 R- read SCSI data register 0140 -W write SCSI data register 0141 R- SCSI status register (see #P0501) 0141 -W SCSI control register (see #P0502) 0142 R- TMC status register (see #P0503) 0142 -W interrupt control register (see #P0504) 0143 R- FIFO status register, TMC-18C50/18C30/36C70 chips only 0143 -W SCSI mode control register (see #P0505) 0144 R- interrupt condition register, TMC-18C50/18C30/36C70 only (see #P0506) 0144 -W TMC control register (see #P0507) 0145 R- ID code LSB register 27h for TMC-1800 chip E9h for TMC-18C50/18C30/36C70 chips 0145 -W memory control register, TMC-18C50/18C30/36C70 only 0146 R- ID code MSB register 60h for TMC-18C50/18C30 chips 61h for TMC-1800 chip 0147 R- read loopback register 0147 -W write loopback register 0148 RW SCSI data no ACK register 0149 R- interrupt status register (see #P0508) 014A R- configuration register 1 (see #P0509) 014B R- configuration register 2, TMC-18C50/18C30/36C70 only (see #P0510) 014B -W I/O control register, TMC-18C30/36C70 only (see #P0511) 014Cw R- read FIFO data register 014Cw -W write FIFO data register 014Ew R- FIFO data count register Notes: any value written into the write loopback register can be read back from the read loopback register unchanged (this is used by the BIOS to test the controller) reading from read SCSI data register and writing to write SCSI data register causes REQ/ACK handshake to occur automatically, reading and writing the SCSI data no ACK register doesn't SCSI FIFO may be used only for DATA IN / DATA OUT phase transfers on TMC-1800; on TMC-18C50/18C30 it may also be used for COMMAND phase transfers Bitfields for SCSI status register: Bit(s) Description (Table P0501) 7 not BSY 6 not MSG 5 not I/O 4 not C/D 3 not REQ 2 not SEL 1 parity error??? 0 not ATN SeeAlso: #P0502,#P0511 Bitfields for SCSI control register: Bit(s) Description (Table P0502) 7 RST 6 SEL 5 BSY 4 ATN 3 I/O 2 C/D 1 MSG 0 bus enable SeeAlso: #P0501,#P0503,#P0504 Bitfields for TMC status register: Bit(s) Description (Table P0503) 7 bus enabled 6 parity enabled 5 FIFO enabled 4 =1 data are expected to flow out from FIFO to SCSI bus =0 data are expected to flow from SCSI bus into FIFO 3 SCSI reset 2 ??? 1 arbitration complete 0 interrupt request SeeAlso: #P0502 Bitfields for interrupt control register: Bit(s) Description (Table P0504) 7 enable interrupt on REQ 6 enable interrupt on SEL 5 enable arbitration interrupt 4 enable interrupt on ??? 0-3 FIFO threshold (how many 512 byte blocks in FIFO should be full/empty for interrupt to be generated) SeeAlso: #P0502 Bitfields for SCSI mode control register: Bit(s) Description (Table P0505) 7 synchronous mode 6 fast SCSI 5-4 reserved? 3-0 synchronous transfer period in 25 ns units SeeAlso: #P0502 Bitfields for interrupt condition register: Bit(s) Description (Table P0506) 7 FIFO error interrupt 6 forced interrupt??? 5 interrupt on RST 4 arbitration interrupt 3 interrupt on SEL 2 interrupt on REQ 1 interrupt on ??? 0 ??? SeeAlso: #P0502 Bitfields for TMC control register: Bit(s) Description (Table P0507) 7 enable FIFO 6 =1 data are expected to flow out from FIFO to SCSI bus =0 data are expected to flow from SCSI bus into FIFO 5 clear forced interrupt, TMC-18C50/18C30/36C70 only 4 enable interrupt 3 enable parity 2 arbitrate 1 force interrupt??? 0 clear SCSI reset flag??? SeeAlso: #P0502 Note: on the TMC-1800 the FIFO must be enabled and bit 6 must be set according to the expected data direction before a data phase will occur (the TMC-1800 probably doesn't generate interrupts on REQ in DATA IN / DATA OUT phases); on the TMC-18C50/18C30 it may be done when the interrupt on REQ occurs and the SCSI phase is DATA IN, DATA OUT or COMMAND Bitfields for interrupt status register: Bit(s) Description (Table P0508) 7 interrupt on REQ enabled 6 interrupt on SEL enabled 5 arbitration interrupt enabled 4 interrupt on ??? enabled 3 interrupt enabled 2 ??? 1 always set??? 0 ??? SeeAlso: #P0502 Bitfields for configuration register 1: Bit(s) Description (Table P0509) 7-6 BIOS address range 00 C8000h-C9FFFh 01 CA000h-CBFFFh 10 CE000h-CFFFFh 11 DE000h-DFFFFh 5-4 I/O address range 00 140h-14Fh 01 150h-15Fh 10 160h-16Fh 11 170h-17Fh 3-1 interrupt select 000 IRQ3 001 IRQ5 010 IRQ10 011 IRQ11 100 IRQ12 101 IRQ14 110 IRQ15 111 no IRQ 0 reserved??? Note: the seven on-board configuration jumpers are read through this register SeeAlso: #P0502,#P0510 Bitfields for configuration register 2: Bit(s) Description (Table P0510) 7 32-bit mode enabled (TMC-18C30/36C70 only???) 6-2 ??? 1 RAM disabled (TMC-18C30/36C70 only???) 0 ??? Note: 256 byte on-chip RAM is mapped at offset 1F00h within the BIOS segment SeeAlso: #P0502,#P0509 Bitfields for TMC control register: Bit(s) Description (Table P0511) 7 enable 32-bit mode 6-0 ??? SeeAlso: #P0502 --------d-P0140014F-------------------------- PORT 0140-014F - Quantum ISA-200S/250MG SCSI adapter Range: alternate address at 0150, 0160, 0170 Note: Quantum ISA-200S/250MG SCSI adapters are based upon Future Domain TMC-18C50 SCSI controller (???) SeeAlso: PORT 0140h-014Fh"Future Domain TMC-16x0" ----------P01400157-------------------------- PORT 0140-0157 - RTC (alternate Real Time Clock for XT) (1st at 0340-0357) --------d-P0140015F-------------------------- PORT 0140-015F - Adaptec AHA-152x SCSI adapter Range: alternate address at 0340 ----------P0150015F-------------------------- PORT 0150-015F - Xirlink/Relialogic XL-220/221 SCSI adapter Range: alternate address at 0140, 0160, 0170 ----------P0150015F-------------------------- PORT 0150-015F - Future Domain TMC-16x0 SCSI adapter Range: alternate address at 0140, 0160, 0170 --------d-P0150015F-------------------------- PORT 0150-015F - Quantum ISA-200S/250MG SCSI adapter Range: alternate address at 0140, 0160, 0170 Note: Quantum ISA-200S/250MG SCSI adapters are based upon Future Domain TMC-18C50 SCSI controller (???) SeeAlso: PORT 0140h-014Fh"Future Domain TMC-16x0" ----------P015C015D-------------------------- PORT 015C-015D - Dell Enhanced Parallel Port SeeAlso: PORT 002Eh,PORT 026Eh,PORT 0398h 015C -W index for data port 015D RW EPP command data ----------P015F------------------------------ PORT 015F - ARTEC Handyscanner A400Z. alternate address at 35F. ----------P0160016F-------------------------- PORT 0160-016F - Xirlink/Relialogic XL-220/221 SCSI adapter Range: alternate address at 0140, 0150, 0170 ----------P0160016F-------------------------- PORT 0160-016F - Future Domain TMC-16x0 SCSI adapter Range: alternate address at 0140, 0150, 0170 --------d-P0160016F-------------------------- PORT 0160-016F - Quantum ISA-200S/250MG SCSI adapter Range: alternate address at 0140, 0150, 0170 Note: Quantum ISA-200S/250MG SCSI adapters are based upon Future Domain TMC-18C50 SCSI controller (???) SeeAlso: PORT 0140h-014Fh"Future Domain TMC-16x0" ----------P0168016F-------------------------- PORT 0168-016F - 4th (Quaternary) EIDE Controller Range: 01F0-01F7 for primary controller, 0170-0177 for secondary controller SeeAlso: PORT 0170h-0177h,PORT 01E8h-01EFh,PORT 01F0h-01F7h ----------P01700176-------------------------- PORT 0170-0176 - OPTi "Vendetta" (82C750) CHIPSET - SECONDARY IDE CONTROLLER Note: to unlock access to these ports, you must perform two immediately successive 16-bit INs from PORT 0171h, followed by 8-bit OUT of 03h to PORT 172h SeeAlso: PORT 01F0h"Vendetta" 0170 RW read cycle timing register (see #P0536) 0171 RW write cycle timing register (see #P0537) 0172 RW internal ID register (see #P0538) 0173 RW control register (see #P0539) 0175 RW strap register (see #P0540) 0176 RW miscellaneous register (see #P0541) ----------P01700177-------------------------- PORT 0170-0177 - HDC 2 (2nd Fixed Disk Controller) (ISA, EISA) Range: 01F0-01F7 for primary controller, 0170-0177 for secondary controller SeeAlso: PORT 0168h-016Fh,PORT 01E8h-01EFh,PORT 01F0h-01F7h ----------P0170017F-------------------------- PORT 0170-017F - Xirlink/Relialogic XL-220/221 SCSI adapter Range: alternate address at 0140, 0150, 0160 ----------P0170017F-------------------------- PORT 0170-017F - Future Domain TMC-16x0 SCSI adapter Range: alternate address at 0140, 0150, 0160 --------d-P0170017F-------------------------- PORT 0170-017F - Quantum ISA-200S/250MG SCSI adapter Range: alternate address at 0140, 0150, 0160 Note: Quantum ISA-200S/250MG SCSI adapters are based upon Future Domain TMC-18C50 SCSI controller (???) SeeAlso: PORT 0140h-014Fh"Future Domain TMC-16x0" ----------P01780179-------------------------- PORT 0178-0179 - Power Management SeeAlso: PORT 0026h,#P0377 0178 -W index selection for data port 0179 RW power management data ----------P0178017F-------------------------- PORT 0178-017F - PC radio by CoZet Info Systems Range: The I/O address range is dipswitch selectable from: 038-03F and 0B0-0BF 078-07F and 0F0-0FF 138-13F and 1B0-1BF 178-17F and 1F0-1FF 238-23F and 2B0-2BF 278-27F and 2F0-2FF 338-33F and 3B0-3BF 378-37F and 3F0-3FF Notes: All of these addresses show a readout of FFh in initial state. Once started, all of the addresses show FBh, whatever might happen. ----------P01CE01CF-------------------------- PORT 01CE-01CF - ATI Mach32 video chipset - ??? 01CE -W index register 01CF RW data register ----------P01E801EF-------------------------- PORT 01E8-01EF - Headland HL21 & Acer M5105 chipsets - SYSTEM CONTROL 01ED RW select internal register. Data to/from 01EF 01EE R- ??? 01EF RW register value 05h = 1000xxxx for low CPU clock speed (4MHz on Morse/Mitac) = 0xxxxxxx for high CPU clock speed (16MHz on Morse/Mitac) 10h memory size bits 2-0 = size (undefined,512K,640K,1024K,2560K,2048K,4096K,undef.) 14h ??? bit 2: 384K RAM of first 1024K relocated to top of memory ----------P01E801EF-------------------------- PORT 01E8-01EF - 3rd (Tertiary) EIDE Controller Range: 01F0-01F7 for primary controller, 0170-0177 for secondary controller SeeAlso: PORT 0168h-016Fh,PORT 0170h-0177h,PORT 01F0h-01F7h ----------P01F001F7-------------------------- PORT 01F0-01F7 - HDC 1 (1st Fixed Disk Controller) (ISA, EISA) Range: 01F0-01F7 for primary controller, 0170-0177 for secondary controller SeeAlso: PORT 0170h-0177h,PORT 3510h-3513h 01F0 RW data register 01F1 R- error register (see #P0512) 01F1 -W WPC/4 (Write Precompensation Cylinder divided by 4) 01F2 RW sector count 01F3 RW sector number (CHS mode) logical block address, bits 0-7 (LBA mode) 01F4 RW cylinder low (CHS mode) logical block address, bits 15-8 (LBA mode) 01F5 RW cylinder high (CHS mode) logical block address, bits 23-16 (LBA mode) 01F6 RW drive/head (see #P0513) 01F7 R- status register (see #P0514) 01F7 -W command register (see #P0515) Bitfields for Hard Disk Controller error register: Bit(s) Description (Table P0512) ---diagnostic mode errors--- 7 which drive failed (0 = master, 1 = slave) 6-3 reserved 2-0 error code 001 no error detected 010 formatter device error 011 sector buffer error 100 ECC circuitry error 101 controlling microprocessor error ---operation mode--- 7 bad block detected 6 uncorrectable ECC error 5 reserved 4 ID found 3 reserved 2 command aborted prematurely 1 track 000 not found 0 DAM not found (always 0 for CP-3022) SeeAlso: #P0513,#P0514 Bitfields for hard disk controller drive/head specifier: Bit(s) Description (Table P0513) 7 =1 6 LBA mode enabled, rather than default CHS mode 5 =1 4 drive select (0 = drive 0, 1 = drive 1) 3-0 head select bits (CHS mode) logical block address, bits 27-24 (LBA mode) SeeAlso: #P0512,#P0514 Bitfields for hard disk controller status register: Bit(s) Description (Table P0514) 7 controller is executing a command 6 drive is ready 5 write fault 4 seek complete 3 sector buffer requires servicing 2 disk data read successfully corrected 1 index - set to 1 each disk revolution 0 previous command ended in an error SeeAlso: #P0512,#P0515 (Table P0515) Values for hard disk controller command codes: Command Spec Type Proto Description class: 00h opt nondata NOP 08h device reset 1xh opt nondata recalibrate 1 20h req PIOin read sectors with retry 1 21h req PIOin read sectors without retry 1 22h req PIOin read long with retry 1 23h req PIOin read long without retry 1 30h req PIOout write sectors with retry 2 31h req PIOout write sectors without retry 2 32h req PIOout write long with retry 2 33h req PIOout write long without retry 2 3Ch IDE opt PIOout write verify 3 40h req nondata read verify sectors with retry 1 41h req nondata read verify sectors without retry 1 50h req vend format track 2 7xh req nondata seek 1 8xh IDE vendor vend vendor unique 3 90h req nondata execute drive diagnostics 1 91h req nondata initialize drive parameters 1 92h opt PIOout download microcode 94h E0h IDE opt nondata standby immediate 1 95h E1h IDE opt nondata idle immediate 1 96h E2h IDE opt nondata standby 1 97h E3h IDE opt nondata idle 1 98h E5h IDE opt nondata check power mode 1 99h E6h IDE opt nondata set sleep mode 1 9Ah IDE vendor vend vendor unique 1 A0h ATAPI packet command A1h ATAPI opt PIOin ATAPI Identify (see #P0524) B0h SMART opt Self Mon., Analysis, Rept. Tech. (see #P0527) C0h-C3h IDE vendor vend vendor unique 2 C4h IDE opt PIOin read multiple 1 C5h IDE opt PIOout write multiple 3 C6h IDE opt nondata set multiple mode 1 C7h ATA-4 Read DMA O/Q C8h IDE opt DMA read DMA with retry 1 C9h IDE opt DMA read DMA without retry 1 CAh IDE opt DMA write DMA with retry 3 CBh IDE opt DMA write DMA w/out retry 3 CCh ATA-4 Write DMA O/Q DAh get media status DBh ATA-2 opt vend acknowledge media chng [Removable] DCh ATA-2 opt vend Boot / Post-Boot [Removable] DDh ATA-2 opt vend Boot / Pre-Boot (ATA-2) [Removable] DEh ATA-2 opt vend door lock [Removable] DFh ATA-2 opt vend door unlock [Removable] E0h-E3h (second half of commands 94h-96h) E4h IDE opt PIOin read buffer 1 E5h-E6h (second half of commands 98h-99h) E8h IDE opt PIOout write buffer 2 E9h IDE opt PIOout write same 3 EAh ATA-3 opt Secure Disable [Security Mode] EAh ATA-3 opt Secure Lock [Security Mode] EAh ATA-3 opt Secure State [Security Mode] EAh ATA-3 opt Secure Enable WriteProt [Security Mode] EBh ATA-3 opt Secure Enable [Security Mode] EBh ATA-3 opt Secure Unlock [Security Mode] ECh IDE req PIOin identify drive 1 (see #P0516) EDh ATA-2 opt nondata media eject [Removable] EEh ATA-3 opt identify device DMA (see #P0516) EFh IDE opt nondata set features 1 (see #P0535) F0h-F4h IDE vend EATA standard F1h Security Set Password F2h Security Unlock F3h Security Erase Prepare F4h Security Erase Unit F5h-FFh IDE vendor vend vendor unique 4 F5h Security Freeze Lock F6h Security Disable Password SeeAlso: #P0512,#P0514 Format of IDE/ATA Identify Drive information: Offset Size Description (Table P0516) 00h WORD general configuration (see #P0517) 02h WORD number of logical cylinders 04h WORD reserved 06h WORD number of logical heads 08h WORD vendor-specific (obsolete: unformatted bytes per track) 0Ah WORD vendor-specific (obsolete: unformatted bytes per sector) 0Ch WORD number of logical sectors 0Eh WORD vendor-specific 10h WORD vendor-specific 12h WORD vendor-specific 14h 10 WORDs serial number no serial number if first word is 0000h else blank-padded ASCII serial number 28h WORD vendor-specific [buffer type: 01h single-sector, 02h multisector, 03h multisector with read cache] 2Ah WORD controller buffer size in 512-byte sectors 0000h = unspecified 2Ch WORD number of vendor-specific (usually ECC) bytes on Read/Write Long; 0000h = unspecified 2Eh 4 WORDs firmware revision no revision number if first word is 0000h else blank-padded ASCII revision number 36h 20 WORDs model number no model number if first word is 0000h else blank-padded ASCII model string 5Eh WORD read/write multiple support bits 7-0: maximum number of sectors per block supported 00h if read/write multiple not supported bits 15-8: vendor-specified 60h WORD able to do doubleword transfers if nonzero 62h WORD capabilities (see #P0518) 64h WORD security mode bit 15: security-mode feature set supported bits 14-8: maximum number of passwords supported 66h WORD PIO data transfer cycle timing 68h WORD single-word DMA data transfer cycle timing 6Ah WORD field validity bit 0: offsets 6Ch-75h valid bit 1: offsets 80h-8Dh valid 6Ch WORD logical cylinders in current translation mode 6Eh WORD logical heads in current translation mode 70h WORD logical sectors per track in current translation mode 72h DWORD current capacity in sectors (excluding device-specific uses) 76h WORD multiple-sector support bits 7-0: count for read/write multiple command bit 8: multiple-sector setting is valid 78h DWORD total number of user-addressable sectors (LBA mode) 00000000h if LBA mode not supported 7Ch WORD single-word DMA transfer modes low byte is bitmap of supported modes (bit 0 = mode 0, etc.) high bytes is bitmap of active mode (bit 8 = mode 0, etc.) 7Eh WORD multiword DMA transfer low byte is bitmap of supported modes (bit 0 = mode 0, etc.) high byte is bitmap of active mode (bit 8 = mode 0, etc.) 80h WORD supported flow control PIO transfer modes 82h WORD minimum multiword DMA transfer cycle time in ns 84h WORD recommended multiword DMA cycle time in ns 86h WORD minimum non-flow-control PIO transfer cycle time in ns 88h WORD minimum PIO transfer cycle time with IORDY in ns 8Ah 2 WORDs reserved for future PIO modes (0) 8Eh 2 WORDs reserved (0) 92h WORD command queueing/overlapped operation (see #P0523) 94h 6 WORDs reserved (0) A0h WORD major revision number of specification to which device conforms 01h = ATA-1, 02h = ATA-2, etc. 0000h/FFFFh = not reported A2h WORD minor revision number of specification to which device conforms 0000h/FFFFh = not reported A4h WORD feature set support 1 (see #P0519) (only valid if revision reported in A0h/A2h) A6h WORD feature set support 2 (see #P0520) (only valid if revision reported in A0h/A2h) A8h WORD (ATA/ATAPI-4) feature set support extension (see #P0521) AAh WORD feature set enabled 1 (see #P0522) (only valid if revision reported in A0h/A2h) ACh WORD feature set enabled 2 (see #P0520) (only valid if revision reported in A0h/A2h) AEh WORD (ATA/ATAPI-4) feature set enabled extension (see #P0521) B0h 42 WORDs reserved (0) 100h 32 WORDs vendor-specific 100h WORD security status 140h 96 WORDs reserved (0) SeeAlso: #P0524,#00267 Bitfields for IDE general configuration: Bit(s) Description (Table P0517) 15 device class =0 ATA device =1 ATAPI device 14 requires format speed tolerance gap 13 supports track offset option 12 supports data strobe offset 11 disk rotational sped tolerance > 0.5% 10-8 disk transfer rate 001 <= 5Mbit/sec 010 5-10 Mbit/sec 100 > 10Mbit/sec 7-6 drive type 01 fixed media 10 removable media 5 synchronized drive motor option enabled 4 head-switching time > 15 microseconds 3 encoding =0 MFM 2-1 sector type 01 hard-sectored 10 soft-sectored 0 unused (0) SeeAlso: #P0516 Bitfields for IDE capabilities: Bit(s) Description (Table P0518) 13 Standby Timer values used according to ATA standard 11 IORDY supported 10 device can disable use of IORDY 9 LBA mode supported 8 DMA supported SeeAlso: #P0516 Bitfields for ATA feature set support 1: Bit(s) Description (Table P0519) 15 Identify Device DMA command is supported 14 NOP (00h) command is supported 13 Read Buffer command is supported 12 Write Buffer command is supported 11 Write Verify command is supported 10 host protected area feature set is supported 9 Device Reset (08h) command is supported 8 Service interrupt is supported 7 release interrupt is supported 6 device supports look-ahead 5 device supports write cache 4 PACKET command feature set is supported 3 power management is supported 2 removable-media feature set is supported 1 security feature set is supported 0 SMART feature set is supported Note: values of 0000h and FFFFh indicate that this field is not supported SeeAlso: #P0516,#P0520,#P0521 Bitfields for ATA feature set support/enabled 2: Bit(s) Description (Table P0520) 15 must be 0 if this field is supported 14 must be 1 if this field is supported 13-2 reserved 1 Read DMA O/Q (C7h) and Write DMA O/Q (CCh) commands supported/enabled 0 Download Microcode (92h) command is supported/enabled SeeAlso: #P0516,#P0522,#P0519,#P0521 Bitfields for ATA feature set support extension: Bit(s) Description (Table P0521) 15 must be 0 if this field is supported 14 must be 1 if this field is supported 13-0 reserved SeeAlso: #P0516,#P0519,#P0520 Bitfields for ATA feature set enabled 1: Bit(s) Description (Table P0522) 15 Identify Device DMA command is supported 14 NOP (00h) command is supported 13 Read Buffer command is supported 12 Write Buffer command is supported 11 Write Verify command is supported 10 host protected area feature set is supported 9 Device Reset (08h) command is supported 8 Service interrupt is enabled 7 release interrupt is enabled 6 look-ahead is enabled 5 write cache is enabled 4 PACKET command feature set is enabled 3 power management is enabled 2 removable-media feature set is enabled 1 security feature set is enabled 0 SMART feature set is enabled SeeAlso: #P0516,#P0520 Bitfields for ATA/ATAPI-4 command queueing/overlapped operation support: Bit(s) Description (Table P0523) 15 reserved 14 device supports command queueing 13 device supports overlapped operation 12-5 reserved 4-0 maximum depth of queued commands supported (0 if bit 14 clear) SeeAlso: #P0516 Format of ATAPI Identify Information: Offset Size Description (Table P0524) 00h WORD general configuration (see #P0525) 02h 9 WORDs ??? 14h 10 WORDs serial number no serial number if first word is 0000h else blank-padded ASCII serial number 28h 3 WORDs vendor-specific 2Eh 4 WORDs firmware revision no revision number if first word is 0000h else blank-padded ASCII revision number 36h 20 WORDs model number no model number if first word is 0000h else blank-padded ASCII model string 5Eh WORD vendor-specific 60h WORD reserved (0) 62h WORD capabilities (see #P0518) 64h WORD security mode??? 66h WORD PIO data transfer cycle timing 68h WORD single-word DMA data transfer cycle timing 6Ah WORD field validity bit 0: offsets 6Ch-73h valid bit 1: offsets 80h-8Dh valid 6Ch WORD ??? logical cylinders in current translation mode 6Eh WORD ??? logical heads in current translation mode 70h WORD ??? logical sectors per track in current translation mode 72h 2 WORDs ??? current capacity in sectors 76h WORD ??? multiple-sector count for read/write multiple command 78h 2 WORDs ??? total number of user-addressable sectors (LBA mode) 7Ch WORD single-word DMA transfer modes low byte is bitmap of supported modes (bit 0 = mode 0, etc.) high bytes is bitmap of active mode (bit 8 = mode 0, etc.) 7Eh WORD multiword DMA transfer low byte is bitmap of supported modes (bit 0 = mode 0, etc.) high bytes is bitmap of active mode (bit 8 = mode 0, etc.) 80h WORD supported flow control PIO transfer modes 82h WORD minimum multiword DMA transfer cycle time 84h WORD recommended multiword DMA cycle time 86h WORD minimum non-flow-control PIO transfer cycle time 88h WORD minimum PIO transfer cycle time with IORDY 8Ah 2 WORDs reserved for future PIO modes (0) 8Eh WORD typical time for release when processing overlapped CMD in microseconds 90h WORD ??? 92h WORD major ATAPI version number 94h WORD minor ATAPI version number 96h 54 WORDs reserved (0) 100h 32 WORDs vendor-specific 140h 96 WORDs reserved (0) SeeAlso: #P0516 Bitfields for ATAPI General Configuration: Bit(s) Description (Table P0525) 15-14 device type 0x not ATAPI 10 ATAPI 11 reserved 13 reserved 12 device present (non-ATAPI) 12-8 ATAPI device type (see #P0526) 7 device is removable 6-5 CMD DMA Request type 00 microprocessor DRQ 01 interrupt DRQ 10 accelerated DRQ 11 reserved 4-2 reserved 1-0 CMD packet size (00 = 12 bytes, 01 = 16 bytes) SeeAlso: #P0524 (Table P0526) Values for ATAPI device type: 00h direct-access device (i.e. disk drive) 01h sequential-access device (i.e. tape drive) 02h printer 03h processor 04h write-once device 05h CD-ROM 06h scanner 07h optical memory 08h medium changer 09h communications device 0Ah reserved for ACS IT8 0Bh reserved for ACS IT8 0Ch array controller device (i.e. RAID) 0Dh-1Eh reserved 1Fh unknown type or no device SeeAlso: #P0525 (Table P0527) Values for Self-Monitoring, Analysis, Reporting Technology (SMART) subcommand: D0h Read Attribute Values (optional) (see #P0529) results returned in 512-byte sector read from controller D1h Read Attribute Thresholds (optional) (see #P0528) results returned in 512-byte sector read from controller D2h Disable Attribute Autosave (optional) sector-count register set to 0000h D2h Enable Attribute Autosave sector-count register set to 00F1h D3h Save Attribute Values (optional) D4h execute off-line tests immediately (optional) D5h-D6h reserved D7h vendor-specific D8h Enable SMART Operations D9h Disable SMART Operations DAh Return SMART Status if any threshold(s) exceeded, CylinderLow set to F4h and CylinderHigh set to 2Ch DBh Enable/Disable Automatic Off-Line Data Collection sector-count register set to 0000h to disable, 00F8h to enable DCh-DFh reserved E0h-EFh vendor-specific Note: to access SMART commands, the Cylinder Low register must be set to 004Fh and the Cylinder High register must be set to 00C2h before invoking the SMART command with the SMART command number in the Features register SeeAlso: #P0515 Format of S.M.A.R.T. attribute thresholds sector: Offset Size Description (Table P0528) 00h WORD data structure revision number (0005h for SMART Revision 2.0) 02h 12 BYTEs attribute threshold data 1 (see #P0531) ... 14Eh 12 BYTEs attribute threshold data 30 (see #P0531) 16Ah 18 BYTEs reserved (0) 17Ch 131 BYTEs vendor-specific 1FFh BYTE checksum (two's complement of eight-bit sum of first 511 bytes) Note: if the drive provides fewer than 30 attributes, all remaining attribute records are filled with NUL (00h) bytes SeeAlso: #P0527,#P0529 Format of S.M.A.R.T. attribute values sector: Offset Size Description (Table P0529) 00h WORD 02h 12 BYTEs attribute value data 1 (see #P0532) ... 14Eh 12 BYTEs attribute value data 30 (see #P0532) 16Ah BYTE off-line data collection status (see #P0533) 16Bh BYTE vendor-specific 16Ch WORD time to complete off-line data collection, in seconds 0001h-FFFFh 16Eh BYTE vendor-sepcific 16Fh BYTE off-line data collection capability (see #P0534) 170h WORD S.M.A.R.T. capabilities (see #P0530) 172h 16 BYTEs reserved (0) 182h 125 BYTEs vendor-specific 1FFh BYTE checksum (two's complement of eight-bit sum of first 511 bytes) Note: if the drive provides fewer than 30 attributes, all remaining attribute records are filled with NUL (00h) bytes SeeAlso: #P0527,#P0528 Bitfields for S.M.A.R.T capabilities: Bit(s) Description (Table P0530) 0 attributes saved on going into power-saving mode 1 Enable/Disable Attribute Autosave subcommands are supported 2-15 reserved SeeAlso: #P0529 Format of S.M.A.R.T. attribute threshold: Offset Size Description (Table P0531) 00h BYTE attribute ID (01h-FFh) 01h BYTE attribute threshold 00h always passing 01h minimum threshold value FDh maximum threshold value FEh invalid (do not use) FFh always failing (for testing) 02h 10 BYTEs reserved (0) Note: the attribute ID and actual threshold values are vendor-specific SeeAlso: #P0528,#P0532 Format of S.M.A.R.T attribute value: Offset Size Description (Table P0532) 00h BYTE attribute ID (01h-FFh) 01h WORD status flags bit 0: pre-failure/advisory =0 value < threshold indicates usage/age exceeding design life =1 value < threshold indicates pre-failure condition bit 1: on-line data collection bits 2-5 vendor-specific bits 6-15 reserved 03h BYTE attribute value (01h-FDh) initial value prior to data collection is 64h 04h 8 BYTEs vendor-specific SeeAlso: #P0529,#P0531 (Table P0533) Values for S.M.A.R.T. off-line data collection status: 00h off-line collection never started 01h reserved 02h off-line data collection completed successfully 03h reserved 04h off-line data collection suspended by command from host 05h off-line data collection aborted by command from host 06h off-line data collection aborted due to fatal error 07h-3Fh reserved 40h-7Fh vendor-specific 80h off-line collection never started (auto-offline feature enabled) 81h reserved 82h off-line data collection completed successfully (auto-offline feature enabled) 83h reserved 84h off-line data collection suspended by command from host (auto-offline feature enabled) 85h off-line data collection aborted by command from host (auto-offline feature enabled) 86h off-line data collection aborted due to fatal error (auto-offline feature enabled) 87h-BFh reserved C0h-FFh vendor-specific SeeAlso: #P0529,#P0534 Bitfields for S.M.A.R.T. off-line data collection capabilities: Bit(s) Description (Table P0534) 0 Execute Off-Line Immediate (D4h) subcommand is implemented 1 Enable/Disable Automatic Off-Line subcommand is implemented 2 abort/resume on interrupting command =0 off-line resumes automatically after an interrupting command =1 off-line collection is aborted by an interrupting command 3-7 reserved SeeAlso: #P0527 (Table P0535) Values for Feature Code: 01h [opt] 8-bit instead of 16-bit data transfers 02h [opt] enable write cache 03h set transfer mode as specified by Sector Count register 04h [opt] enable all automatic defect reassignment 22h [opt] Write Same, user-specified area 33h [opt] disable retries 44h specify length of ECC bytes used by Read Long and Write Long 54h [opt] set cache segments (value in Sector Count register) 55h disable look-ahead 66h disable reverting to power-on defaults 77h [opt] disable ECC 81h [opt] 16-bit instead of 8-bit data transfers 82h [opt] disable write cache 84h [opt] disable all automatic defect reassignment 88h [opt] enable ECC 99h [opt] enable retries 9Ah [opt] set device maximum average current AAh enable look-ahead ABh [opt] set maximum prefecth (value in Sector Count register) BBh use four bytes of ECC on Read Long and Write Long (for compat.) CCh enable reverting to power-on defaults DDh [opt] Write Same, entire disk SeeAlso: #00266 ----------P01F001F6-------------------------- PORT 01F0-01F6 - OPTi "Vendetta" (82C750) CHIPSET - PRIMARY IDE CONTROLLER Note: to unlock access to these ports, you must perform two immediately successive 16-bit INs from PORT 01F1h, followed by 8-bit OUT of 03h to PORT 1F2h SeeAlso: PORT 0170h"Vendetta",PORT 01F0h"HDC 1" 01F0 RW read cycle timing register (see #P0536) 01F1 RW write cycle timing register (see #P0537) 01F2 RW internal ID register (see #P0538) 01F3 RW control register (see #P0539) 01F5 RW strap register (see #P0540) 01F6 RW miscellaneous register (see #P0541) Bitfields for OPTi "Vendetta" IDE controller read cycle timing register: Bit(s) Description (Table P0536) 7-4 DRD# pulse width - 1 LCLKs on 16-bit IDE data register read 3-0 recovery time between DRD# and DA2-0/DCSx# - 2 LCLKs after 16-bit IDE data register read Notes: if register 1F6h/176h bit 0 = 0, controls drive selected by register 1F3h/173h bits 3-2 if register 1F6h/176h bit 0 = 1, controls drive not selected by register 1F3h/173h bits 3-2, if register 1F3h/173h bit 7 = 1 SeeAlso: #P0537,#P0538,#P0539 Bitfields for OPTi "Vendetta" IDE controller write cycle timing register: Bit(s) Description (Table P0537) 7-4 DWR# pulse width - 1 LCLKs on 16-bit IDE data register write 3-0 recovery time between DWR# and DA2-0/DCSx# - 2 LCLKs after 16-bit IDE data register write Notes: if register 1F6h/176h bit 0 = 0, controls drive selected by register 1F3h/173h bits 3-2 if register 1F6h/176h bit 0 = 1, controls drive not selected by register 1F3h/173h bits 3-2, if register 1F3h/173h bit 7 = 1 SeeAlso: #P0536,#P0539 Bitfields for OPTi "Vendetta" IDE controller internal ID register: Bit(s) Description (Table P0538) 7 controller register access disable (write-only) 6 controller register access disable until power-down or reset (write-only) 5-2 reserved (read-only) 1-0 reserved (11, otherwise all controller register writes blocked) SeeAlso: #P0540 Bitfields for OPTi "Vendetta" IDE controller control register: Bit(s) Description (Table P0539) 7 enable 1F0h-1F1h/170h-171h and 1F6h/176h bits 5-1 cycle timing set for drive not selected by 1F3h/173h bits 3-2 6-5 reserved (read-only) 4 (primary IDE controller) minimum read wait states 0 = 2 wait states 1 = 1 wait states (secondary IDE controller) reserved 3 enable 1F0h-1F1h/170h-171h cycle timing set for drive 1 2 enable 1F0h-1F1h/170h-171h cycle timing set for drive 0 1 reserved 0 reserved (1) (read-only) SeeAlso: #P0540,#P0541 Bitfields for OPTi "Vendetta" IDE controller strap register: Bit(s) Description (Table P0540) 7 reserved (1) (read-only) 6-5 revision number (read-only) 11 = chip revision in PCI configuration register 08h (see #00878) (see #00931) 4 (primary IDE controller) DINTR state (read-only) (secondary IDE controller) SDINTR state (read-only) 3-2 (primary IDE controller only) IDE device cycle time (read-only) value determined by PCI config register 40h bits 1-0 (see #00931) 1 reserved (1) (read-only) 0 (primary IDE controller only) PCI CLK 0 = 33 MHz 1 = 25 MHz SeeAlso: #P0539,#P0541,#P0538 Bitfields for OPTi "Vendetta" IDE controller miscellaneous register: Bit(s) Description (Table P0541) 7 reserved 6 read prefetch enable 5-4 address setup time between DRD#/DWR# active and DA2-0/DCS3#/DCS1# - 1 LCLKs 3-1 minimum number of LCLKs between DRDY# high and DRD#/DRW# inactive - 2 0 cycle timing register switch (1F0h/170h and 1F1h/171h) SeeAlso: #P0539,#P0540 ----------P01F8------------------------------ PORT 01F8 - ??? 01F8 RW ??? bit 0: A20 gate control (set = A20 enabled, clear = disabled) ----------P01F901FF-------------------------- PORT 01F9-01FF - PC radio by CoZet Info Systems Range: The I/O address range is dipswitch selectable from: 038-03F and 0B0-0BF 078-07F and 0F0-0FF 138-13F and 1B0-1BF 178-17F and 1F0-1FF 238-23F and 2B0-2BF 278-27F and 2F0-2FF 338-33F and 3B0-3BF 378-37F and 3F0-3FF Notes: All of these addresses show a readout of FFh in initial state. Once started, all of the addresses show FBh, whatever might happen. --------d-P0200------------------------------ PORT 0200 - Digidesign 'Session 8' HARD-DISK RECORDING SYSTEM SeeAlso: PORT 0300h"Digidesign" ----------P0200020F-------------------------- PORT 0200-020F - Game port reserved I/O address space 0200-0207 - Game port, eight identical addresses on some boards 0201 R- read joystick position and status (see #P0542) 0201 -W fire joystick's four one-shots 0201 RW gameport on mc-soundmachine, mc 03-04/1992: Adlib-compatible, Covox 'voice master' & 'speech thing' compatible soundcard. (enabled if bit1=1 in PORT 038Fh. Because it is disabled on power-on, it cannot be found by BIOS) (see PORT 0388h-038Fh) Bitfields for joystick position and status: Bit(s) Description (Table P0542) 7 status B joystick button 2 / D paddle button 6 status B joystick button 1 / C paddle button 5 status A joystick button 2 / B paddle button 4 status A joystick button 1 / A paddle button 3 B joystick Y coordinate / D paddle coordinate 2 B joystick X coordinate / C paddle coordinate 1 A joystick Y coordinate / B paddle coordinate 0 A joystick X coordinate / A paddle coordinate ----------P020002FF-------------------------- PORT 0200-02FF - Sunshine uPW48, programmer for EPROM version CPU's 8748/8749 Range: 4 bit DIP switch installable in the range 20x-2Fx 0200-0203 addresses of the 8255 on the uPW48 0208-020B addresses of ??? on the uPW48 (all showing zeros) ----------P02080209-------------------------- PORT 0208-0209 - Intel 82C212B "Neat" chipset - EMS emulation control Range: may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, 02E8 ----------P0208020A-------------------------- PORT 0208-020A - Chips&Technologies 82C235 "SCAT" chipset - EMS PAGE REGISTERS Range: PORT 0208h or PORT 0218h, depending on configuration register 4Fh (see #P0067) SeeAlso: PORT 0022h"82C235" 0208 RW EMS page register 0209 RW EMS page register 020A RW EMS page register ----------P020C020F-------------------------- PORT 020C-020F - AIMS LAB PC Radio Range: configurable to PORT 020Ch or PORT 030Ch Notes: writing a value with bit 3 set to one of these ports turns on the radio; writing a value with bit 3 clear turns it off PORT 020Eh bits 1 indicates status of some kind ----------P02100217-------------------------- PORT 0210-0217 - Expansion unit (XT) 0210 -W latch expansion bus data 0210 R- verify expansion bus data 0211 -W clear wait, test latch 0211 R- High byte data address 0212 R- Low byte data address 0213 -W 0=enable, 1=disable expansion unit 0214 -W latch data (receiver card port) 0214 R- read data (receiver card port) 0215 R- High byte of address, then Low byte (receiver card port) ----------P02100211-------------------------- PORT 0210-0211 - Game Blaster Range: PORT 02x0h-02x1h, x=1,2,... 0210 -W register index 0211 ?W register data ----------P02180219-------------------------- PORT 0218-0219 - Intel 82C212B "Neat" chipset - EMS emulation control Range: base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8 ----------P0218021A-------------------------- PORT 0218-021A - Chips&Technologies 82C235 "SCAT" chipset - EMS PAGE REGISTERS Range: PORT 0208h or PORT 0218h, depending on configuration register 4Fh (see #P0067) SeeAlso: PORT 0022h"82C235" 0218 RW EMS page register 0219 RW EMS page register 021A RW EMS page register ----------P02200223-------------------------- PORT 0220-0223 - Sound Blaster / Adlib port (Stereo) SeeAlso: PORT 0388h-0389h 0220 R- Left speaker -- Status port 0220 -W Left speaker -- Address port 0221 -W Left speaker -- Data port 0222 R- Right speaker -- Status port 0222 -W Right speaker -- Address port 0223 -W Right speaker -- Data port ----------P02200227-------------------------- PORT 0220-0227 - Soundblaster PRO and SSB 16 ASP ----------P02200228-------------------------- PORT 0220-0228 - C&T 82C570 CHIPSlink '3270' Protocol Controller !!!chips\82c570.pdf p.7 ----------P0220022F-------------------------- PORT 0220-022F - Soundblaster PRO 2.0 ----------P0220022F-------------------------- PORT 0220-022F - Soundblaster PRO 4.0 Note: the FM music is accessible on 0388/0389 for compatibility. 0220 R- left FM status port 0220 -W left FM music register address port (index) 0221 RW left FM music data port 0222 R- right FM status port 0222 -W right FM music register address port (index) 0223 RW right FM music data port 0224 -W mixer register address port (index) (see #P0543) 0225 RW mixer data port 0226 -W DSP reset 0228 R- FM music status port 0228 -W FM music register address port (index) 0229 -W FM music data port 022A R- DSP read data (voice I/O and Midi) 022C -W DSP write data / write command 022C R- DSP write buffer status (bit 7) 022E R- DSP data available status (bit 7) (Table P0543) Values for SB Mixer register index: Index Description PORT 0225h data 00h reset 00h = zero all mixer controls 04h voice select high nybble = left, low nybble = right 0Ah microphone gain bits 2-0 = gain 22h master gain high nybble = left, low nybble = right 26h MIDI gain high nybble = left, low nybble = right 28h CD gain high nybble = left, low nybble = right 2Eh Line In high nybble = left, low nybble = right 30h Master Left bits 7-3 = volume 31h Master Right bits 7-3 = volume 32h Voice Left bits 7-3 = volume 33h Voice Right bits 7-3 = volume 34h MIDI Left bits 7-3 = volume 35h MIDI Right bits 7-3 = volume 36h CD Left bits 7-3 = volume 37h CD Right bits 7-3 = volume 38h LineIn Left bits 7-3 = volume 39h LineIn Right bits 7-3 = volume 3Ah Microphone bits 7-3 = gain 3Bh PC speaker bits 7-3 = volume 3Ch Sound Output highest set bit is enabled source (see #P0544) 3Dh Sound Source (left) highest set bit is enabled source (see #P0544) 3Eh Sound Source (right) highest set bit is enabled source (see #P0544) 40h In gain bits 7-6 = gain (00 = x1, 01 = x2, 10 = x4, 11 = x8) 41h Out gain (left) bits 7-6 = gain (as for In) 42h Out gain (right) bits 7-6 = gain (as for In) 43h Automatic Gain Control bit 0 = enable 44h Treble (left) bits 7-3 = volume 45h Treble (right) bits 7-3 = volume 46h Bass (left) bits 7-3 = volume 47h Bass (right) bits 7-3 = volume Bitfields for SB Mixer sound source: Bit(s) Description (Table P0544) 7 PC speaker??? 6 MIDI left 5 MIDI right 4 LineIn left 3 LineIn right 2 CD left 1 CD right 0 microphone Note: bits 7-5 are ignored for Sound Output register SeeAlso: #P0543 ----------P022B------------------------------ PORT 022B - GI1904 Scanner Interface Adapter Range: PORT 026Bh, PORT 02ABh (default), PORT 02EBh, PORT 032Bh, PORT 036Bh Range: PORT 03ABh, PORT 03EBh ----------P022C------------------------------ PORT 022C - GS-IF Scanner Interface adapter Range: PORT 022Ch, PORT 026Ch, PORT 02ACh, PORT 02ECh (default), PORT 032Ch, PORT 036Ch, PORT 03ACh, PORT 03ECh Note: many SPI 400dpi/800dpi gray / H/T handy scanner by Marstek, Mustek and others use this interface ----------P022F------------------------------ PORT 022F - mc-soundmachine, mc 03-04/1992 - SPEECH I/O Note: An Adlib-compatible Covox 'voice master' & 'speech thing' compatible soundcard SeeAlso: PORT 0378h"Covox",PORT 0388h-038Fh"soundmachine" 022F RW Covox compatible speech I/O (via internal A/D converter, each read access starts a new conversion cycle) register enabled if bit7=1 in PORT 038Fh ----------P02300233-------------------------- PORT 0230-0233 - Adaptec 154xB/154xC SCSI adapter. Range: four ports at any of 0130, 0134, 0230, 0234, 0330 (default) or 0334 ----------P02340237-------------------------- PORT 0234-0237 - Adaptec 154xB/154xC SCSI adapter. Range: four ports at any of 0130, 0134, 0230, 0234, 0330 (default) or 0334 ----------P0238023F-------------------------- PORT 0238-023F - COM port addresses on UniRAM card by German magazine c't selectable from 238, 2E8, 2F8, 338, 3E0, 3E8, 3F8 ----------P0238023B-------------------------- PORT 0238-023B - Bus Mouse Port (secondary address) InstallCheck: read the ID Port twice; if installed, the first byte returned will be DEh, and the second will vary by card (revision number???) Note: secondary address for bus mice from MS and Logitech, and the ATI video adapter mouse SeeAlso: PORT 023Ch"Mouse" 0238 ?W Command port 0239 ?W Data port 023A R? ID Port ----------P023C023F-------------------------- PORT 023C-023F - Bus Mouse Port (primary address) InstallCheck: read the ID Port twice; if installed, the first byte returned will be DEh, and the second will vary by card (revision number???) Note: primary address for bus mice from MS and Logitech, the ATI video adapter mouse, and the Commodore PC30III bus mouse SeeAlso: PORT 0238h"Mouse" 023C ?W Command port 023D ?W Data port 023E R? ID Port ----------P0240024F-------------------------- PORT 0240-024F - Gravis Ultra Sound by Advanced Gravis Range: The I/O address range is dipswitch selectable from: 0200-020F and 0300-030F 0210-021F and 0310-031F 0220-022F and 0320-032F 0230-023F and 0330-033F 0240-024F and 0340-034F 0250-025F and 0350-035F 0260-026F and 0360-036F 0270-027F and 0370-037F SeeAlso: PORT 0340h-034Fh,PORT 0746h 0240 -W Mix Control register (see #P0545) 0241 R- Read Data 0241 -W Trigger Timer 0246 R- IRQ Status Register (see #P0546) 0248 RW Timer Control Reg Same as ADLIB Board (see PORT 0200h) 0249 -W Timer Data (see #P0547) 024B -W IRQ Control Register (0240 bit 6 = 1) (see #P0548) 024B -W DMA Control Register (0240 bit 6 = 0) (see #P0549) 024F RW Register Controls (rev 3.4+) Bitfields for Gravis Ultra Sound mix control register: Bit(s) Description (Table P0545) 6 Control Register Select (see 024B) 5 Enable MIDI Loopback 4 Combine GF1 IRQ with MIDI IRQ 3 Enable Latches 2 Enable MIC IN 1 Disable LINE OUT 0 Disable LINE IN SeeAlso: #P0546 Bitfields for Gravis Ultra Sound IRQ status register: Bit(s) Description (Table P0546) 7 DMA TC IRQ 6 Volume Ramp IRQ 5 WaveTable IRQ 3 Timer 2 IRQ 2 Timer 1 IRQ 1 MIDI Receive IRQ 0 MIDI Transmit IRQ SeeAlso: #P0545,#P0548,#P0549 Bitfields for Gravis Ultra Sound timer data: Bit(s) Description (Table P0547) 7 Reset Timr IRQ 6 Mask Timer 1 5 Mask Timer 2 1 Timer 2 Start 0 Timer 1 Start SeeAlso: #P0546,#P0548 Bitfields for Gravis Ultra Sound IRQ control register: Bit(s) Description (Table P0548) 6 Combine Both IRQ 5-3 MIDI IRQ Selector 000 No IRQ 001 IRQ 2 010 IRQ 5 011 IRQ 3 100 IRQ 7 101 IRQ 11 110 IRQ 12 111 IRQ 15 2-0 GF1 IRQ Selector 000 No IRQ 001 IRQ 2 010 IRQ 5 011 IRQ 3 100 IRQ 7 101 IRQ 11 110 IRQ 12 111 IRQ 15 SeeAlso: #P0546,#P0549 Bitfields for Gravis Ultra Sound DMA Control Register: Bit(s) Description (Table P0549) 6 Combine Both DMA 5-3 DMA Select Register 2 000 No DMA 001 DMA 1 010 DMA 3 011 DMA 5 100 DMA 6 101 DMA 7 2-0 DMA Select Register 1 000 No DMA 001 DMA 1 010 DMA 3 011 DMA 5 100 DMA 6 101 DMA 7 SeeAlso: #P0546,#P0548,#P0591 ----------P02400257-------------------------- PORT 0240-0257 - RTC (alternate Real Time Clock for XT) (1st at 0340-0357) (used by TIMER.COM v1.2 which is the 'standard' timer program) ----------P02580259-------------------------- PORT 0258-0259 - Intel 82C212B "Neat" chipset - EMS emulation control Range: base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8 ----------P02580259-------------------------- PORT 0258-0259 - AT RAMBANK Memory Expansion Board - EXT MEMORY AND EMS-SUPPORT Range: base address may be set to 0218h, 0228h, 0238h, 0258h, 0268h, 0298h, or 02A8h ----------P0258025F-------------------------- PORT 0258-025F - Intel Above Board ----------P02600268-------------------------- PORT 0260-0268 - LPT port address on the UniRAM card by German magazine c't selectable from 260, 2E0, 2E8, 2F0, 3E0, 3E8. ----------P02680269-------------------------- PORT 0268-0269 - Intel 82C212B "Neat" chipset - EMS emulation control Range: base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8 ----------P026B------------------------------ PORT 026B - GI1904 Scanner Interface Adapter Range: PORT 022Bh, PORT 02ABh (default), PORT 02EBh, PORT 032Bh, PORT 036Bh Range: PORT 03ABh, PORT 03EBh ----------P026C------------------------------ PORT 026C - GS-IF Scanner Interface adapter Range: PORT 022Ch, PORT 026Ch, PORT 02ACh, PORT 02ECh (default), PORT 032Ch, PORT 036Ch, PORT 03ACh, PORT 03ECh Note: many SPI 400dpi/800dpi gray / H/T handy scanner by Marstek, Mustek and others use this interface ----------P026E026F-------------------------- PORT 026E-026F - Dell Enhanced Parallel Port SeeAlso: PORT 002Eh,PORT 015Ch,PORT 0398h 026E -W index for data port 026F RW EPP command data ----------P026E026F-------------------------- PORT 026E-026F - Intel 82091AA Advanced Integrated Peripheral Range: PORT 0022h (X-Bus), PORT 0024h (X-Bus), PORT 026Eh (ISA), or PORT 0398h (ISA) SeeAlso: PORT 0022h"82091AA",PORT 0024h"82091AA",PORT 0398h"82091AA" 026E ?W configuration register index 026F RW configuration register data ----------P0278------------------------------ PORT 0278 - Covox 'Speech Thing' COMPATIBLES SeeAlso: PORT 022Fh"Covox",PORT 0388h-038Fh"soundmachine" 0278 -W speech data output via printer data port (with mc-soundmachine, enabled if bit5=1 in 38F) ----------P0278027A-------------------------- PORT 0278-027A - PARALLEL PRINTER PORT (usually LPT1, sometimes LPT2) Range: usually PORT 03BCh, PORT 0278h, or PORT 0378h SeeAlso: PORT 0278h"EPP",MEM 0040h:0008h,INT 17/AH=00h 0278 -W data port 0279 R- status port (see #P0658 at PORT 03BCh) 027A RW control port (see #P0659 at PORT 03BCh) ----------P0278027F-------------------------- PORT 0278-027F - Intel 82360SL/82091AA - EPP-mode PARALLEL PORT Range: PORT 0278h or PORT 0378h SeeAlso: PORT 0278h"LPT1",PORT 0678h"ECP" 0278-027A as for standard parallel port 027B RW address strobe 027C RW data strobe 0 027D RW data strobe 1 027E RW data strobe 2 027F RW data strobe 3 ----------P0279------------------------------ PORT 0279 - Plug-and-Play - CONFIGURATION REGISTER SeeAlso: PORT 0A79h 0279 -W index into Plug-and-Play register set for Read Data Port and Write Data Port I/O (see #P0550,#P0551) (Table P0550) Values for Plug-and-Play Card-Level Registers: 00h set Read Port address bits 9-2 of Read Data port address (bits 15-10 are always 0, bits 1-0 are always 11); valid Read Port addresses are 0203h-03FFh 01h serial isolation 02h configuration control 03h Wake command (specifies which card is accessed through configuration registers) 04h resource data 05h status 06h Card Select Number (CSN) 07h logical device number (selects which logical device on card is accessed at locations 30h-FFh) (see #P0551) 08h-1Fh reserved 20h-2Fh vendor-specific Note: there is one set of these registers per installed card SeeAlso: #P0551 (Table P0551) Values for Plug-and-Play Logical Device Registers: 30h activate bit 0: device is active on ISA bus bits 7-1: reserved (0) 31h I/O range check bit 0: I/O Read Pattern select (if bit 1 set, then I/O reads return 55h if this bit is set, AAh if this bit is clear) bit 1: I/O Range Check Enable: if set, all reads from device I/O registers return 55h or AAh, depending on bit 0 bits 7-2: reserved (0) 32h-37h reserved 38h-3Fh vendor-specific 40h-44h 24-bit ISA memory descriptor 0 45h-47h reserved 48h-4Ch 24-bit ISA memory descriptor 1 4Dh-4Fh reserved 50h-54h 24-bit ISA memory descriptor 2 55h-57h reserved 58h-5Ch 24-bit ISA memory descriptor 3 5Dh-5Fh reserved 60h-6Fh I/O configuration registers 0-7 70h-71h IRQ channel select 0 72h-73h IRQ channel select 1 74h-75h DMA configuration registers 0-1 76h-7Eh 32-bit memory range configuration register 0 7Fh reserved 80h-88h 32-bit memory range configuration register 1 89h-8Fh reserved 90h-98h 32-bit memory range configuration register 2 99h-9Fh reserved A0h-A8h 32-bit memory range configuration register 3 A9h-EFh reserved for logical device configuration F0h-FEh vendor-specific FFh reserved Note: there is one set of these registers per logical device SeeAlso: #P0550 ----------P0280------------------------------ PORT 0280 - LCD display on Wyse 2108 PC ----------P02800288-------------------------- PORT 0280-0288 - non-standard COM port addresses (V20-XT by German magazine c't) selectable from 0280, 0288, 0290, 0298, 6A0, 6A8 --------s-P02800283-------------------------- PORT 0280-0283 - Pro Audio Spectrum 16 (PAS16) Range: PORT 0280h, PORT 0284h, PORT 0288h, PORT 028Ch, PORT 384h, PORT 0388h (default), or PORT 038Ch ----------P0288028F-------------------------- PORT 0288-028F - non-standard COM port addresses (V20-XT by German magazine c't) 0280-0288 selectable from 0280, 0288, 0290, 0298, 06A0, 06A8 0290-0298 0298-029F --------s-P02840287-------------------------- PORT 0284-0287 - Pro Audio Spectrum 16 (PAS16) Range: PORT 0280h, PORT 0284h, PORT 0288h, PORT 028Ch, PORT 384h, PORT 0388h (default), or PORT 038Ch --------s-P0288028F-------------------------- PORT 0288-028F - Pro Audio Spectrum 16 (PAS16) Range: PORT 0280h, PORT 0284h, PORT 0288h, PORT 028Ch, PORT 384h, PORT 0388h (default), or PORT 038Ch --------s-P028C028F-------------------------- PORT 028C-028F - Pro Audio Spectrum 16 (PAS16) Range: PORT 0280h, PORT 0284h, PORT 0288h, PORT 028Ch, PORT 384h, PORT 0388h (default), or PORT 038Ch ----------P02A002A7-------------------------- PORT 02A0-02A7 - Sunshine EW-901BN, EW-904BN EPROM writer card (release 1986) for EPROMs up to 27512 02A0-02A3 addresses of the 8255 on the EW-90xBN ----------P02A202A3-------------------------- PORT 02A2-02A3 - MSM58321RS clock ----------P02A802A9-------------------------- PORT 02A8-02A9 - Intel 82C212B "Neat" chipset - EMS emulation control Range: base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8 ----------P02AB------------------------------ PORT 02AB - GI1904 Scanner Interface Adapter (default) Range: PORT 022Bh, PORT 026Bh, PORT 02EBh, PORT 032Bh, PORT 036Bh Range: PORT 03ABh, PORT 03EBh Note: the GI1904 is used by many SPI 400/800dpi gray/halftone/color handy scanners by Marstek, Mustek, Conrad, V”lkner and others ----------P02AC------------------------------ PORT 02AC - GS-IF Scanner Interface adapter Range: PORT 022Ch, PORT 026Ch, PORT 02ACh, PORT 02ECh (default), PORT 032Ch, PORT 036Ch, PORT 03ACh, PORT 03ECh Note: many SPI 400dpi/800dpi gray / H/T handy scanner by Marstek, Mustek and others use this interface ----------P02B002BF-------------------------- PORT 02B0-02BF - Trantor SCSI adapter ----------P02B002DF-------------------------- PORT 02B0-02DF - alternate EGA, primary EGA at 03C0 ----------P02B802B9-------------------------- PORT 02B8-02B9 - Intel 82C212B "Neat" chipset - EMS emulation control Range: base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8 ----------P02C002Cx-------------------------- PORT 02C0-02Cx - AST-clock ----------P02C002DF-------------------------- PORT 02C0-02DF - XT-Real Time Clock 2 (default jumpered address) ----------P02C002CF-------------------------- PORT 02C0-02CF - EGA (2nd adapter) SeeAlso: PORT 03C0h --------V-P02C602C9-------------------------- PORT 02C6-02C9 - VGA/MCGA - DAC REGISTERS (alternate address) Range: PORT 03C6h or PORT 02C6h (alternate) SeeAlso: PORT 03C6h ----------P02D002DA-------------------------- PORT 02D0-02DA - C&T 82C570 CHIPSlink '3270' Protocol Controller !!!chips\82c570.pdf p.12 ----------P02E002E8-------------------------- PORT 02E0-02E8 - LPT port address on the UniRAM card by German magazine c't Range: base address selectable from 0260, 02E0, 02E8, 02F0, 03E0, and 03E8. ----------P02E002EF-------------------------- PORT 02E0-02EF - GPIB (General Purpose Interface Bus, IEEE 488 interface) (GAB 0 on XT) 02E1 ?? GPIB (adapter 0) 02E2 02E3 ----------P02E002EF-------------------------- PORT 02E0-02EF - data aquisition (AT) 02E2 ?? data aquisition (adapter 0) 02E3 ?? data aquisition (adapter 0) ----------P02E8------------------------------ PORT 02E8 - S3 86C928 video controller (ELSA Winner 1000) ----------P02E802E9-------------------------- PORT 02E8-02E9 - Intel 82C212B "Neat" chipset - EMS emulation control Range: base address may be set to 0208, 0218, 0258, 0268, 02A8, 02B8, or 02E8 ----------P02E802EF-------------------------- PORT 02E8-02EF - serial port, same as 02F8, 03E8 and 03F8 (COM4) ----------P02E802EF-------------------------- PORT 02E8-02EF - 8514/A and compatible (e.g. ATI Graphics Ultra) 02E8 R- display status 02E8 -W horizontal total 02EA RW Lookup: DAC mask 02EB -W Lookup: DAC read index 02EC -W Lookup: DAC write index 02ED RW Lookup: DAC data ----------P02EA------------------------------ PORT 02EA - S3 86C928 video controller (ELSA Winner 1000) ----------P02EB------------------------------ PORT 02EB - GI1904 Scanner Interface Adapter Range: PORT 022Bh, PORT 026Bh, PORT 02ABh (default), PORT 032Bh, PORT 036Bh, PORT 03ABh, PORT 03EBh ----------P02EC------------------------------ PORT 02EC - GS-IF Scanner Interface adapter Range: PORT 022Ch, PORT 026Ch, PORT 02ACh, PORT 02ECh (default), PORT 032Ch, PORT 036Ch, PORT 03ACh, PORT 03ECh Note: many SPI 400dpi/800dpi gray / H/T handy scanner by Marstek, Mustek and others use this interface ----------P02F002F8-------------------------- PORT 02F0-02F8 - LPT port address on the UniRAM card by German magazine c't selectable from 260, 2E0, 2E8, 2F0, 3E0, 3E8. ----------P02F802FF-------------------------- PORT 02F8-02FF - serial port, same as 02E8, 03E8 and 03F8 (COM2) 02F8 -W transmitter holding register 02F8 R- receiver buffer register 02F8 RW divisor latch, low byte when DLAB=1 02F9 RW divisor latch, high byte when DLAB=1 02F9 RW interrupt enable register when DLAB=0 02FA R- interrupt identification register 02FB RW line control register 02FC RW modem control register 02FD R- line status register 02FF RW scratch register ----------P0300------------------------------ PORT 0300 - Award POST Diagnostic SeeAlso: PORT 0080h --------d-P0300------------------------------ PORT 0300 - Digidesign 'Session 8' HARD-DISK RECORDING SYSTEM SeeAlso: PORT 0200h"Digidesign" --------s-P03000301-------------------------- PORT 0300-0301 - MPU-401 MIDI UART Range: alternate address at PORT 0330h, occasionally at PORT 0310h or PORT 0320h ----------P03000301-------------------------- PORT 0300-0301 - Soundblaster 16 ASP MPU-Midi EMULATION ----------P0300????-------------------------- PORT 0300-???? - HP IEC/HP-IB adapter (e.g. for use with tape streamer HP9142) ----------P03000303-------------------------- PORT 0300-0303 - Panasonic 52x CD-ROM SCSI Miniport Range: PORT 0300h-0303h,PORT 0320h-0323h,PORT 0340h-0343h,PORT 0360h-0363h, and PORT 0380h-0383h ----------P0300030F-------------------------- PORT 0300-030F - Philips CD-ROM player CM50 ----------P0300030F-------------------------- PORT 0300-030F - CompaQ Tape drive adapter. alternate address at 0100 --------N-P0300031F-------------------------- PORT 0300-031F - 3com Ethernet adapters (default address) --------N-P0300031F-------------------------- PORT 0300-031F - NE2000 compatible Ethernet adapters Range: may be placed at 0300h, 0320h, 0340h, or 0360h SeeAlso: PORT 0300h"PCnet" --------N-P0300031F-------------------------- PORT 0300-031F - AMD PCnet - NE2100-compatible Ethernet adapters Range: may be placed at 0300h, 0320h, 0340h, or 0360h, with the card's ROM appearing at segment C800h, CC00h, D000h, or D400h, respectively Note: for the PCnet-FAST chip, the I/O address may be read from the PCI configuration space at offset 10h (see #00878 at INT 1A/AX=B10Ah) SeeAlso: PORT 0300h"NE2000",#00878 0300-030F R- address PROM (used to store Ethernet address, etc.) 0310w RW Register Data Port (RDP) (see #P0552,#P0553) 0312w ?W Register Access Port (RAP) (selects register index for RDP and IDP) (see #P0570) 0314w ?W Reset 0316w RW ISA Bus Data Port (IDP) 0318w reserved for vendor-specific use 031A-031F reserved (Table P0552) Values for AMD PCnet-ISA Register Data Port index: 00h "CSR0" status and control flags (see #P0554) 01h "CSR1" low half of IADR (appears at PORT 0316h) 02h "CSR2" high half of IADR (appears at PORT 0317h) 03h "CSR3" interrupt masks (see #P0555) 04h "CSR4" interrupt masks and status bits (see #P0556) 08h-0Bh logical address filter 0Ch-0Eh physical address register 0Fh "CSR15" mode (see #P0560) 4Ch "CSR76" receive descriptor ring length 4Eh "CSR78" transmit descriptor ring length 50h "CSR80" FIFO threshold / DMA burst control (see #P0564) 52h "CSR82" DMA bus timer 58h "CSR88" chip ID 70h "CSR112" number of missed packets 72h "CSR114" number of receive collisions 7Ch "CSR124" BMU test register bit 4: accept runt packets SeeAlso: #P0570,#P0553 (Table P0553) Values for AMD PCnet-SCSI/PCnet-FAST Register Data Port index: 00h "CSR0" status and control flags (see #P0554) 01h "CSR1" low half of IADR (appears at PORT 0316h) 02h "CSR2" high half of IADR (appears at PORT 0317h) 03h "CSR3" interrupt masks (see #P0555) 04h "CSR4" interrupt masks and status bits (see #P0556) 05h "CSR5" (PCnet-FAST) extended control and interrupt 1 (see #P0557) 06h "CSR6" receive/transmit descriptor table lengths (see #P0558) 07h "CSR7" (PCnet-FAST) extended control and interrupt 2 (see #P0559) 08h-0Bh logical address filter 0Ch-0Eh physical address register 0Fh "CSR15" mode (see #P0560) 10h "CSR16" alias of CSR1 11h "CSR17" alias of CSR2 12h "CSR18" low half of current receive buffer address 13h "CSR19" high half of current receive buffer address 14h "CSR20" low half of current transmit buffer address 15h "CSR21" high half of current transmit buffer address 16h "CSR22" low half of next receive buffer address 17h "CSR23" high half of next receive buffer address 18h "CSR24" low half of receive-ring base address 19h "CSR25" high half of receive-ring base address 1Ah "CSR26" low half of next receive descriptor address 1Bh "CSR27" high half of next receive descriptor address 1Ch "CSR28" low half of current receive descriptor address 1Dh "CSR29" high half of current receive descriptor address 1Eh "CSR30" low half of transmit ring base address 1Fh "CSR31" high half of transmit ring base address 20h "CSR32" low half of next transmit descriptor address 21h "CSR33" high half of next transmit descriptor address 22h "CSR34" low half of current transmit descriptor address 23h "CSR35" high half of current transmit descriptor address 24h "CSR36" low half of next next receive descriptor address 25h "CSR37" high half of next next receive descriptor address 26h "CSR38" low half of next next transmit descriptor address 27h "CSR39" high half of next next transmit descriptor address 28h "CSR40" current receive byte count (see #P0561) 29h "CSR41" current receive status 2Ah "CSR42" current transmit byte count (see #P0562) 2Bh "CSR43" current transmit status 2Ch "CSR44" next receive byte count (bits 11-0; bits 15-12=0) 2Dh "CSR45" next receive status 2Eh "CSR46" transmit poll time counter 2Fh "CSR47" transmit polling interval 30h "CSR48" receive poll time counter 31h "CSR49" receive polling interval 32h-39h reserved 3Ah "CSR58" software style (see #P0563) 3Bh reserved 3Ch "CSR60" previous transmit descriptor address (low) 3Dh "CSR61" previous transmit descriptor address (high) 3Eh "CSR62" previous transmit byte count (bits 11-0; bits 15-12=0) 3Fh "CSR63" previous transmit status 40h "CSR64" next transmit buffer address (low) 41h "CSR65" next transmit buffer address (high) 42h "CSR66" next transmit byte count (bits 11-0; bits 15-12=0) 43h "CSR67" next transmit status 44h-47h reserved 48h "CSR72" receive ring counter 49h reserved 4Ah "CSR74" transmit ring counter 4Bh reserved 4Ch "CSR76" receive descriptor ring length 4Dh reserved 4Eh "CSR78" transmit descriptor ring length 4Fh reserved 50h "CSR80" FIFO threshold / DMA burst control (see #P0564) 51h reserved 52h "CSR82" (PCnet-SCSI) DMA bus timer (PCnet-FAST) transmit descriptor address (low) 53h reserved 54h "CSR84" DMA address register (low) 55h "CSR85" DMA address register (high) 56h "CSR86" buffer byte counter (bits 11-0; bits 15-12=0) 57h reserved 58h "CSR88" chip ID (low 16 bits) (see #P0565) 59h "CSR89" chip ID (high 16 bits) (see #P0565) 5Ah "CSR90" (PCnet-SCSI) 5Bh reserved 5Ch "CSR92" ring length conversion 5Dh reserved 5Eh "CSR94" (PCnet-SCSI) 5Fh-63h reserved 64h "CSR100" bus timeout 65h-6Fh reserved 70h "CSR112" number of missed packets 71h reserved 72h "CSR114" number of receive collisions 73h-79h reserved 7Ah "CSR122" advanced feature control (see #P0566) 7Bh reserved 7Ch "CSR124" BMU test register (see #P0567) 7Dh "CSR125" (PCnet-FAST) MAC Enhanced Configuration Control (see #P0568) 7Eh-7Fh reserved SeeAlso: #P0552,#P0594 Bitfields for AMD PCnet CSR0 status and control flags: Bit(s) Description (Table P0554) 15 "ERR" error; set if BABL, CERR, MISS, or MESS set 14 "BABL" network babbling control 13 "CERR" collision error 12 "MISS" missed frame 11 "MERR" memory error 10 "RINT" receive interrupt 9 "TINT" transmit interrupt 8 "IDON" initialization done 7 "INTR" interrupt flag 6 "IENA" interrupt enable 5 "RXON" recieve ON 4 "TXON" transmit ON 3 "TDMD" transmit demand 2 "STOP" stop -- disable all external activity 1 "STRT" start -- enable extrnal activity 0 "INIT" begin initialization procedure SeeAlso: #P0552,#P0555 Bitfields for AMD PCnet CSR3 interrupt masks: Bit(s) Description (Table P0555) 15 reserved 14 "BABLM" disable babble interrupt 13 reserved 12 "MISSM" disable missed-frame interrupt 11 "MERM" disable memory-error interrupt 10 "RINTM" disable receive interrupt 9 "TINTM" disable transmit interrupt 8 "IDONM" disable initialization-done interrupt 7-5 reserved 4 "DXMT2PD" disable Transmit Two Part Deferral 3 "EMBA" enable modified back-off algorithm 2-0 reserved Note: other bits are reserved SeeAlso: #P0552,#P0554,#P0556 Bitfields for AMD PCnet CSR4 interrupt masks and status bits: Bit(s) Description (Table P0556) 15 "ENTST" enable Test Mode / CSR124 access 14 "DMAPLUS" disable CSR80 burst transaction counter 13 "TIMER" enable Bus Timer register 12 "DPOLL" disable transmit polling 11 "APADXMT" Auto-Pad Transmit 10 "ASTRPRCV" enable automatic pad stripping 9 "MFCO" missed frame counter has overflowed 8 "MFCOM" disable interrupt on MFCO 7 "UINTCMD" (PCnet-FAST) user interrupt command 6 "UINT" (PCnet-FAST) user interrupt pending write 1 to clear 5 "RCVCCO" receive collision counter has overflowed 4 "RCVCCOM" disable interrupt on RCVCCO 3 "TXSTRT" Transmit Start 2 "TXSTRTM" disable interrupt on TXSTRT 1 "JAB" Jabber error 0 "JABM" disable interrupt on JAB SeeAlso: #P0552,#P0555,#P0553 Bitfields for AMD PCnet-FAST CSR5 extended control and interrupt 1: Bit(s) Description (Table P0557) 31-16 reserved 15 "TOKINTD" disable Transmit OK interrupt 14 "LTINTEN" enable Last Transmit interrupt 13-12 reserved 11 "SINT" System Interrupt (write 1 to clear) 10 "SINTE" enable System Interrupt 9 "SLPINT" Sleep Interrupt (write 1 to clear) 8 "SLPINTE" enable Sleep Interrupt 7 "EXDINT" Excessive Deferral Interrupt (write 1 to clear) 6 "EXDINTE" enable Excessive Deferral Interrupt 5 "MPPLBA" Magic Packet Physical Logical Broadcast Accept 4 "MPINT" Magic Packet Interrupt (write 1 to clear) 3 "MPINTE" enable Magic Packet Interrupt 2 "MPEN" enable Magic Packet mode 1 "MPMODE" Magic Packet mode active 0 "SPND" Suspend SeeAlso: #P0553,#P0556,#P0559 Bitfields for AMD PCnet CSR6 Descriptor Table Length register: Bit(s) Description (Table P0558) 15-12 transmit encoded ring length 11-8 receive encoded ring length 7-0 reserved SeeAlso: #P0553,#P0557 Bitfields for AMD PCnet CSR7 Extended Control and Interrupt 2: Bit(s) Description (Table P0559) 15 "FASTSPNDE" enable Fast Suspend 14 "RXFRTG" Receive Frame Tag 13 "RDMD" Receive Demand 12 "RXDPOL" disable receive polling 11 "STINT" Software Timer Interrupt (write 1 to clear) 10 "STINTE" enable Software Timer Interrupt 9 "MREINT" MII Management Read Error Interrupt (write 1 to clear) 8 "MREINTE" enable MII Management Read Error Interrupt 7 "MAPINT" MII Management Auto-Poll Interrupt (write 1 to clear) 6 "MAPINTE" enable MII Management Auto-Poll Interrupt 5 "MCCINT" MII Management Command Complete Interrupt (write 1 to clr) 4 "MCCINTE" enable MII Management Command Complete Interrupt 3 "MCCIINT" MII Management Command Complete Internal Interrupt (write 1 to clear) 2 "MCCIINTE" enable MII Manamagement Command Complete Internal Int. 1 "MIIPDTINT" MII PHY Detect Transition Interrupt (write 1 to clear) 0 "MIIPDTINTE" enable MII PHY Detect Transition Interrupt SeeAlso: #P0553,#P0557 Bitfields for AMD PCnet CSR15 mode flags: Bit(s) Description (Table P0560) 15 "PROM" promiscuous mode 14 "DRCVBC" disable Receive Broadcast 13 "DRCVPA" disable Receive Physical Address 12 "DLNKTST" disable Link Status 11 "DAPC" disable Automatic Polarity Correction 10 "MENDECL" MENDEC loopback mode 9 "LRT/TSEL" Low Receive Threshold 8-7 "PORTSEL" Port Select 00 AUI 01 10Base-T 10 GPSI 11 reserved 6 "INTL" internal loopback 5 "DRTY" disable retry 4 "FCOLL" force collision 3 "DXMTFCS" disable Transmit CRC 2 "LOOP" enable Loopback 1 "DTX" disable transmitter 0 "DRX" disable receiver SeeAlso: #P0552,#P0556,#P0564 Bitfields for AMD PCnet CSR40 Current Receive Byte Count register: Bit(s) Description (Table P0561) 15-12 reserved (0) 11-0 current receive byte count (copy of BCNT field of current receive descriptor's RMD1) SeeAlso: #P0553,#P0562 Bitfields for AMD PCnet CSR42 Current Transmit Byte Count register: Bit(s) Description (Table P0562) 15-12 reserved (0) 11-0 current transmit byte count (copy of BCNT field of current receive descriptor's TMD1) SeeAlso: #P0553,#P0561 Bitfields for AMD PCnet CSR58 Software Style register: Bit(s) Description (Table P0563) 15-11 reserved (undefined) 10 "APERREN" enabled advanced parity error handling 9 "CSRPCNET" PCnet-ISA compatibility (read-only) 8 "SSIZE32" 32-bit software structures for data blocks 7-0 "SWSTYLE" software style 00h LANCE/PCnet-ISA (16-bit software structures) 01h reserved 02h PCnet-PCI (32-bit software) 03h PCnet-PCI (32-bit software) SeeAlso: #P0553 Bitfields for AMD PCnet CSR80 FIFO threshold and DMA burst control: Bit(s) Description (Table P0564) 15-14 reserved 13-12 receive FIFO high-water mark; request DMA when N byte available 00 = 16 bytes 01 = 32 bytes 10 = 64 bytes 11-10 transmit starting point; start transmission after N bytes written 00 = 4 bytes 01 = 16 bytes 10 = 64 bytes 11 = 112 bytes 9-8 transmit FIFO low-water mark; start DMA when room for N bytes 00 = 8 bytes 01 = 16 bytes 10 = 32 bytes 7-0 DMA burst register SeeAlso: #P0552,#P0560 Bitfields for AMD PCnet Chip ID register (read-only): Bit(s) Description (Table P0565) 31-28 hardware version 27-12 part number 2623h = Am79C971 11-1 manufacturer ID (0001h = AMD) 0 reserved (1) SeeAlso: #P0553 Bitfields for AMD PCnet CSR122 Advanced Feature Control register: Bit(s) Description (Table P0566) 15-1 reserved 0 "RCVALGN" DWORD-align received packets SeeAlso: #P0553,#P0567 Bitfields for AMD PCnet CSR124 Test Register 1: Bit(s) Description (Table P0567) 15-5 reserved 4 (PCnet-SCSI) accept runt packets 3 (PCnet-FAST) accept runt packets 2-0 reserved SeeAlso: #P0553,#P0566 Bitfields for AMD PCnet-FAST CSR125 MAC Enhanced Configuration Control reg: Bit(s) Description (Table P0568) 15-8 inter-packet gap (reducing from default 96 can disrupt network) 7-0 inter-frame spacing, part 1 SeeAlso: #P0553 (Table P0569) Values for AMD PCnet-ISA ISA Bus Configuration Register index: 00h "MSRDA" width of DMA read signal 01h "MSWRA" width of DMA write signal 02h "MC" ISA bus configuration (see #P0572) 05h "LED1" LED1 signal control (see #P0573) 06h "LED2" LED2 signal control (see #P0573) 07h "LED3" LED3 signal control (see #P0573) SeeAlso: #P0552,#P0594,#P0570 (Table P0570) Values for AMD PCnet-SCSI Bus Configuration Register index: 00h "MSRDA" width of DMA read signal (reserved) 01h "MSWRA" width of DMA write signal (reserved) 02h "MC" miscellaneous configuration (see #P0572) 03h reserved 04h "LINKST" link status 05h "LED1" LED1 signal control (see #P0573) -- receive status 06h "LED2" LED2 signal control (see #P0573) 07h "LED3" LED3 signal control (see #P0573) -- transmit status 08h-0Fh reserved 10h "IOBASEL" 11h "IOBASEU" 12h "BSBC" burst size and bus control 13h "EECAS" EEPROM Control and Status 14h "SWS" software style 15h "INTCON" reserved SeeAlso: #P0553,#P0569,#P0571 (Table P0571) Values for AMD PCnet-FAST Bus Configuration Register index: 00h "MSRDA" width of DMA read signal (reserved) 01h "MSWRA" width of DMA write signal (reserved) 02h "MC" miscellaneous configuration (see #P0572) 03h reserved !!!p.154 04h "LED0" LED0 status 05h "LED1" LED1 signal control (see #P0573) -- receive status 06h "LED2" LED2 signal control (see #P0573) 07h "LED3" LED3 signal control (see #P0573) -- transmit status 08h reserved 09h "FDC" full-duplex control 0Ah-0Fh reserved 10h "IOBASEL" I/O base select (lo) -- reserved 11h "IOBASEU" I/O base select (hi) -- reserved 12h "BSBC" burst size and bus control 13h "EECAS" EEPROM Control and Status 14h "SWS" software style 15h "INTCON" reserved 16h "PCILAT" PCI-bus latency 17h "PCISID" PCI subsystem ID 18h "PCISVID" PCI subsystem vendor ID 19h "SRAMSIZ" SRAM size 1Ah "SRAMB" SRAM boundary 1Bh "SRAMIC" SRAM interface control 1Ch "EBADDRL" expansion bus address (low) 1Dh "EBADDRU" expansion bus address (high) 1Eh "EBD" expansion bus data port 1Fh "STVAL" software timer value 20h "MIICAS" MII control and status 21h "MIIADDR" MII address 22h "MIIMDR" MII management data 23h "PCIVID" PCI vendor ID SeeAlso: #P0553,#P0569,#P0570 Bitfields for AMD PCnet ISA bus configuration: Bit(s) Description (Table P0572) 3 EADISEL 2 AWAKE 1 ASEL 0 XMAUSEL SeeAlso: #P0570,#P0573 Bitfields for AMD PCnet LEDn signal control: Bit(s) Description (Table P0573) 15 LEDOUT 14-8 reserved 7 PSE 6-5 reserved 4 XMTE 3 RVPE 2 RCVE 1 JABE 0 COLE SeeAlso: #P0570 ----------P0300031F-------------------------- PORT 0300-031F - prototype cards Periscope hardware debugger ----------P030C030F-------------------------- PORT 030C-030F - AIMS LAB PC Radio Range: configurable to PORT 020Ch or PORT 030Ch Notes: writing a value with bit 3 set to one of these ports turns on the radio; writing a value with bit 3 clear turns it off PORT 020Eh bits 1 indicates status of some kind --------s-P03100311-------------------------- PORT 0310-0311 - MPU-401 MIDI UART Range: alternate address at PORT 0300h or PORT 0330h, occasionally at PORT 0320h ----------P0310031F-------------------------- PORT 0310-031F - Philips CD-ROM player CM50 --------s-P03200321-------------------------- PORT 0320-0321 - MPU-401 MIDI UART Range: alternate address at PORT 0300h or PORT 0330h, occasionally at PORT 0310h ----------P03200323-------------------------- PORT 0320-0323 - XT HDC 1 (Hard Disk Controller) SeeAlso: PORT 01F0h-01F7h 0320 RW data register 0321 -W reset controller 0321 R- read controller hardware status (see #P0574) 0322 R- read DIPswitch setting on XT controller card 0322 -W generate controller-select pulse 0323 -W write pattern to DMA and INT mask register Bitfields for XT hard disk controller hardware status: Bit(s) Description (Table P0574) 7-6 always 0 5 logical unit number 4-2 always 0 1 error occurred 0 always 0 ----------P03240327-------------------------- PORT 0324-0327 - XT HDC 2 (Hard Disk Controller) ----------P0328032B-------------------------- PORT 0328-032B - XT HDC 3 (Hard Disk Controller) ----------P032B------------------------------ PORT 032B - GI1904 Scanner Interface Adapter Range: PORT 022Bh, PORT 026Bh, PORT 02ABh (default), PORT 02EBh, PORT 036Bh, PORT 03ABh, PORT 03EBh ----------P032C------------------------------ PORT 032C - GS-IF Scanner Interface adapter Range: PORT 022Ch, PORT 026Ch, PORT 02ACh, PORT 02ECh (default), PORT 032Ch, PORT 036Ch, PORT 03ACh, PORT 03ECh Note: many SPI 400dpi/800dpi gray / H/T handy scanner by Marstek, Mustek and others use this interface ----------P032C032F-------------------------- PORT 032C-032F - XT HDC 4 (Hard Disk Controller) ----------P032C032F-------------------------- PORT 032C-032F - AMD InterWave ----------P03300331-------------------------- PORT 0330-0331 - MPU-401 MIDI UART Range: alternate address at PORT 0300h, occasionally at PORT 0310h or PORT 0320h 0330 RW data register 0331 R- status register (see #P0575) 0331 -W command register (see #P0576) Note: MPU-401 genarates an interrupt when MIDI code is ready; by reading MIDI code from the data register this interrupt is cleared Bitfields for MPU-401 status register: Bit(s) Description (Table P0575) 7 input ready =1 no data is available for reading =0 data is available for reading 6 output ready =1 not ready to receive command/data byte =0 ready to receive command/data byte 5-0 reserved Note: pending input seems to block the output SeeAlso: #P0576 (Table P0576) Values for MPU-401 commands (data go to/from PORT 0330h): Command Description Results Parameter 01h send MIDI stop ACK - 02h send MIDI start ACK - 03h send MIDI continue ACK - 15h stop all (recording, ACK - playback and MIDI) 34h return timing bytes ACK - in stop mode 35h enable mode messages ACK - to PC 38h enable system common ACK - messages to PC 39h enable real time ACK - messages to PC 3Ch use CLS sync ACK - 3Dh use SMPTE sync ACK - 3Fh enter UART mode ACK - 80h use MIDI sync ACK - 81h use FSK sync ACK - 82h use MIDI sync ACK - 83h enable metronome ACK - 84h disable metronome ACK - 87h enable pitch and ACK - controller 8Ah disable data in stopped ACK - mode 8Bh enable data in stop mode ACK - 8Ch disable measure end ACK - messages to host 91h enable ext MIDI control ACK - 94h disable clock to host ACK - 95h enable clock to host ACK - 97h enable system exclusive ACK - messages to PC ACh get MIDI version ACK,VER - ADh get revision ACK,REV - Cxh set timebase to x*24 ACK - ppqn (x>1) D0h ??? ACK - DFh ??? ACK - E0h set tempo ACK BPS E4h set clocks per click ACK CPC E6h set beats per measure ACK BPM E7h send all clocks to host ACK 1 byte (04h is sent) FFh reset ACK - Notes: after receiving a command byte MPU-401 must reply with command acknowledge byte FEh in data register command parameters are sent, and response bytes are received through the data register no commands (except reset) can be issued in UART mode, and MPU-401 must be reset to leave UART mode Key: ACK command acknowledge byte (FEh) VER MIDI version number bits 7-4: major version bits 0-3: minor version REV revision number BPS beats per second (8..250) CPC clocks per click BPM beats per measure SeeAlso: #P0576 ----------P03300333-------------------------- PORT 0330-0333 - Adaptec 154xB/154xC SCSI adapter (default address) Range: four ports at any of 0130, 0134, 0230, 0234, 0330 (default) or 0334 Notes: Adaptec AHA-154x adapters use ISA bus-mastering mechanism, and so require the DMA channel to be programmed to the cascaded mode the original AHA-1540 only supported asynchronous SCSI data transfers, and did not support scatter/gather operation AHA-154xA+ supports the target mode implementing the SCSI-2 processor device model; it executes INQUIRY, TEST UNIT READY, and REQUEST SENSE commands received from the initiators without CPU intervention; the CPU is required to provide information only for the SEND/RECEIVE commands; other commands are treated by the host adapter as invalid AHA-154xCF supports Fast SCSI data transfer; AHA-154xCP additionally supports SCSI Configured AutoMagically (SCAM) protocol AHA-174x EISA SCSI adapters in "standard" mode "look like" AHA-154x there was also an AHA-1640, an MCA version of the AHA-154x BusLogic BT-545S and DTC 3290 seem to be "almost" compatible with the Adaptec AHA-154x 0330 R- status register (see #P0577) 0330 -W control register (see #P0578) 0331 R- data in register 0331 -W command / data out register (see #P0580) 0332 R- interrupt status register (see #P0579) 0333 R- (AHA-154xC+) diagnostic register cycles thru bytes 41h,44h,41h,50h when read ("ADAP") Bitfields for AHA-154x status register: Bit(s) Description (Table P0577) 7 self-test in progress (STST) 6 diagnostic failure (DIAGF) 5 mailbox initialization required (INIT) 4 adapter idle (IDLE) 3 command register full (CDF) 2 data register full (DF) 1 reserved 0 invalid command (INVDCMD) Notes: bit 0 is only valid from the time the host adapter command complete interrupt is set (bit 2 in the interrupt flag register) until it is reset the data in register should only be read if bit 2 is set; reading the data in register resets this bit command / data out register should only be written if bit 3 is zero; the host adapter usually clears this bit within 100 mcs after CPU writes to the command / data out register bit 4 indicates that the host adapter has no outstanding adapter or SCSI commands bit 5 indicates that the mailbox initialization command (01h) required bit 7 is asserted after a power-on or hard reset (bit 7 in the control register); when diagnostics is complete, this bit is reset and bit 5 or bit 6 is set to indicate seccessful or unsuccessful completion; if the bit remain set, then initialization/diagnostic could not be completed if bit 6 is set indication failed diagnostics, only the hard reset (bit 7 in the control register) will clear it SeeAlso: #P0578,#P0579,#P0580 Bitfields for AHA-154x control register: Bit(s) Description (Table P0578) 7 hardware reset (HRST) 6 software reset (SRST) 5 interrupt reset (IRST) 4 SCSI bus reset (SCRST) 0-3 reserved Notes: setting bit 4 causes the host adapter to assert the RST signal on the SCSI bus for 25 microseconds (reset hold time); the reset is managed as a SCSI soft reset, and will allow partially completed operations to continue; use bit 7 to force a SCSI hard reset setting bit 5 clears all bits in the interrupt flag register and resets the interrupt setting bit 6 clears all ongoing SCSI and host adapter commands setting bit 7 forces the host adapter into a state identical to a normal power on state: diagnostic functions are executed and all status for ongoing SCSI operations is lost, a reset condition is generated on the SCSI bus; while the reset is being processed, bit 7 on the status register is set when soft/hard reset is complete, bits 4 and 5 of the status register are set SeeAlso: #P0577 Bitfields for AHA-154x interrupt status register: Bit(s) Description (Table P0579) 7 any interrupt (ANYINTR) 4-6 reserved 3 SCSI reset detected (SCRD) 2 host adapter command complete (HACC) 1 mailbox out available (MBOA) 0 mailbox in full (MBIF) Notes: bit 0 indicates that an entry has been placed by the host adapter in the mailbox in; this interrupt should be reset as soon as possible bit 1 indicates that an outbound mailbox entry is now available for use bit 2 indicates that an adapter command has been completed; bit 0 of the status register will indicate success or failure; during the parameter transfers to/from the host adapter, this bit should be examined to verify that the command has not been ended abnormally bit 3 indicates that a SCSI reset has been received on the SCSI bus; CPU can convert the SCSI soft reset to the SCSI hard reset by setting bit 6 of the control register upon the detection of the SCSI reset interrupt; it is not set for the CPU-initiated SCSI reset (via bit 4 of the control register) if the host adapter command complete and SCSI reset detected interrupts are present, the mailbox in full and mailbox out available interrupts are not presented until the former are cleared if bit 7 of this register or bit 2 of the status register is set, host adapter command complete and SCSI reset detected interrupts will not be presented until the interrupts already present are cleared SeeAlso: #P0577,#P0581 (Table P0580) Values for AHA-154x host adapter commands: Command Description Parameters Results 00h no operation - - 01h mailbox initialization MBC,MBA0..MBA2 - 02h start SCSI command - - 03h start PC/AT BIOS command BFN,TRG,CH,CLHH, - HL,SN,SC,BA0..BA2 04h adapter inquiry - BID,SOID,FWR0,FWR1 05h enable mailbox out E/D - interrupt 06h set selection time-out E/D,00h,TO0,TO1 - 07h set bus on time BON - 08h set bus off time BOFF - 09h set AT bus transfer speed ATBS - 0Ah return installed devices - TC0..TC7 0Bh return configuration data - DAP,IC,SID 0Ch enable target mode E/D,LUM - (not AHA-1540/W1542A) 0Dh return setup data DIL SPS,ATBS,BON,BOFF, MBC,MBA0..MBA2, STA0..STA7,DS (see #P9001) 10h intialize SCSI subsystem ??? ??? (AHA-174x in std mode) 11h return formware checksum - CS0,CS1 (AHA-174x in std mode) 1Ah write adapter channel 2 BA0..BA2 - buffer 1Bh read adapter channel 2 BA0..BA2 - buffer 1Ch write adapter FIFO buffer BA0..BA2 - 1Dh read adapter FIFO buffer BA0..BA2 - 1Fh echo command data EV EV 20h run adapter diagnostics - - (AHA-1542B+) 21h set adapter options ESG,DS - 21h set adapter options NOB, adapter opts - (AHA-1542B+) (see #P9005) 22h program EEPROM 00h,NED,SEA, (AHA-1542C+) EEPROM data - (see #P9002) 23h return EEPROM data D/C,NED,EA EEPROM data bytes (AHA-1542C+) (see #P9002) 24h set shadow RAM parameters SRP - (AHA-1542C+) 25h BIOS mailbox initializa- MBC,MBA0..MBA2 - tion (since AHA-1540B rev. 1.4?) 26h set BIOS bank 1 - - (AHA-1542C+) 27h set BIOS bank 2 - - (AHA-1542C+) 28h return extended BIOS - F,MBLT information (since AHA-1540B rev. 1.4?) 29h enable mailbox interface MBU,MBLT - (since AHA-1540B rev. 1.4?) 2Ah ??? (AHA-154xC) - - 2Ch detect termination setting??? (AHA-1542CP) - TS 2Dh detect SCAM devices??? - IDA,??? (AHA-1542CP) 34h set SCSI ID configuration SID,IDC - (AHA-154xCF+) 41h AMI inquiry (AMI-4448) SL C0..C3,M0..M5, S0..S5,V0..V5 (see #P9003) 82h start BIOS SCSI command - - (since AHA-1540B rev. 1.4?) 8Dh exteded setup information DIL? ??? (since AHA-1540B rev. 1.4?) Note: ATBS AT bus transfer speed (see #P9004) 00h,AAh 5.0 MB/s 01h,99h 6.7 Mb/s 02h 8.0 Mb/s 03h,88h 10.0 Mb/s 04h 5.7 Mb/s BBh 4.0 Mb/s? CCh 3.3 Mb/s? DDh 2.9 Mb/s? EEh 2.5 Mb/s? FFh 2.2 Mb/s? BA0..BA2 MSB..LSB of the physical address of the data buffer BFN BIOS function number (00h-04h,08h,09h,0Ch-11h,14h,15h) BID board ID 00h AHA-1540 (16-head BIOS) 20h BusLogic BT-545S 30h AHA-1540 (64-head BIOS) 31h AHA-1540 41h AHA-154xA/154xB (64-head BIOS) 42h AHA-1640 (64-head BIOS) 43h AHA-174x 44h AHA-1542C 45h AHA-1542CF BOFF bus off time (in microseconds) time the adapter stays off the AT bus when transferring data 1..64 mcs, default 4 mcs BON bus on time (in microseconds) time the adapter stays on the AT bus when transferring data 2..15 mcs, default 11 mcs CH bits 7-4: reserved bits 3-0: bits 9-6 of cylinder number CLHH bits 7-2: bits 5-0 of cylinder number bits 1-0: bits 5-4 of head number CS0,CS1 checksum of the standard mode microcode D/C default/current EEPROM data (00h default, 01h current) DAP DRQ arbitration priority bit 7: channel 7 bit 6: channel 6 bit 5: channel 5 bits 4-1: reserved (0) bit 0: channel 0 DIL data in length number of bytes to return (0 means 256 bytes) DS (AHA-154xB+?) disconnect status bit N is set if target ID N is unable to disconnect? E/D enable/diable parameter 00h disable 01h enable EA EEPROM address to read data from ESG 01h: enable scatter/gather EV echo value (to be echoed back) F flags bits 7-4: reserved??? (0) bit 3: extended BIOS translation (255 heads / 63 sectors) bits 2-0: reserved??? (0) FWR0,FWR1 firmware revision (alphanumeric) GS global setting byte bits 7-6: reserved (0) bit 5: enable parity check bit 4: reserved (0) bit 3: enable synchronous transfer bit 2: enable disconnection bits 1-0: reserved (0) HL bits 7-4: reserved bits 3-0: bits 3-0 of head number IDA SCAM IDs assigned bit N is set if a target ID N was assigned to a SCAM device IDC SCSI ID configuration (see #P9006) IRQ interrupt channel bit 7: reserved (0) bit 6: IRQ15 bit 5: IRQ14 bit 4: reserved (0) bit 3: IRQ12 bit 2: IRQ11 bit 1: IRQ10 bit 0: IRQ9 LUM logical unit mask bit N is set if LUN N is to respond in target mode MBA0..MBA2 MSB..LSB of the physical address of the mailbox area (see #P0581) MBC mailboxes count (nonzero), max. 1 for BIOS mailboxes MBLT mailbox lock type 01h translation lock (for extended BIOS) 02h dynamic scan lock others reserved MBU 00h: mailbox unlock NED number of EEPROM data bytes to read/write NOB number of adapter option bytes SC sector count SEA starting EEPROM address SID SCSI ID bits 7-3: reserved (0) bits 2-0: binary value of SCSI ID SL string length SN sector number - 1 SOID special options ID 30h ??? 41h standard model SPS SDT and parity status bits 7-2: reserved (0) bit 1: SCSI parity check enabled bit 0: synchronous negotiation initiated SRP shadow RAM parameters STA0..STA7 synchronous transfer agreements for target ID 0..7 bit 7: synchronous transfer negotiated bits 6-4: value defining synchronous transfer period period in ns can be calculated as 200+50*value bits 3-0: negotiated offset value TC0..TC7 target 0..7 configuration bit M in byte N is set if SCSI ID N LUN M is installed TO0,TO1 MSB, LSB of the time-out value (in ms) default 250 ms TRG bits 7-5: target ID bits 4-0: reserved TS termination setting (see #P9004) Notes: all commands except 02h, 05h, 82h should only be issued if the host adapter is idle (bit 4 in the status register set) command 02h can be issued even if the command / data out register is full (bit 3 in the status register may be set) command 02h causes host adapter to scan both its SCSI and BIOS mailbox areas; command 82h causes host adapter to scan only BIOS mailbox area all commands except 02h and 05h cause host adapter command complete interrupt (bit 2 in the interrupt flag register) after completetion; command 05h will still generate the interrupt if its parameter was invalid return installed devices command (0Ah) results in the host adapter issuing the TEST UNIT READY command to each target/LUN combination return setup data command (0Dh) returns the number of bytes requested with DIL parameter for read/write channel 2 buffer commands (1Bh/1Ah) data buffer must be 64 bytes long; for read/write FIFO buffer commands (1Dh/1Ch) it must be 54 bytes long set adapter options command (21h) takes the number of option bytes specified with NOB parameter BusLogic BT-545S gets the adapter inquiry command (04h) wrong returning only one byte instead of four; DTC 3290 gets this command wrong too AMI inquiry command (41h) returns the number of bytes requested with SL parameter SeeAlso: #P0577,#P0579 (Table P9000) Values for AHA-154x AT bus transfer speed: 00h 5.0 MB/s 01h 6.7 MB/s 02h 8.0 MB/s 03h 10.0 MB/s 04h 5.7 MB/s 88h 10.0 MB/s 99h 6.7 MB/s AAh 5.0 MB/s BBh 4.0 MB/s??? CCh 3.3 MB/s??? DDh 2.9 MB/s??? EEh 2.5 MB/s??? FFh 2.2 or 3.3 MB/s??? SeeAlso: #P0580 Format of AHA-154x setup data: Offset Size Description (Table P9001) 00h BYTE SDT and parity status bits 7-2: reserved (0) bit 1: SCSI parity check enabled bit 0: synchronous negotiation initiated 01h BYTE AT bus transfer speed (see #P9000) 02h BYTE bus on time (in mcs) 03h BYTE bus off time (in mcs) 04h BYTE number of mailboxes (00h = the mailbox initialization command has not yet been successfully completed) 05h 3 BYTEs big-endian physical address of the mailbox area (see #P0581) 08h 8 BYTEs synchronous transfer agreements for target ID 0-7 bit 7: synchronous transfer negotiated bits 6-4: value defining synchronous transfer period period (in ns) can be calculated as 200+50*value bits 3-0: negotiated offset value 10h BYTE (AHA-154xB+?) disconnect status bit N is set if target ID N is unable to disconnect? 11h 20 BYTEs reserved (0) 25h BYTE ??? 26h BYTE ??? 27h WORD ??? (big-endian) 29h 3 BYTEs big-endian physical address of the BIOS mailbox (see #P0581) SeeAlso: #P9002,#P9005,#P0580 Format of AHA-154xC+ EEPROM data: Offset Size Description (Table P9002) 00h BYTE bit 7: (AHA-154xCF) floppy controller I/O port (0 = 3F0h, 1 = 370h) bit 6: ??? bit 5: EDD support enabled bit 4: ??? bit 3: ??? bits 2-0: host adapter SCSI ID 01h BYTE bit 7: ??? bits 6-4: DMA priority (0 and 5-7 are valid) bit 3: ??? bits 2-0: interrupt channel (IRQ) (IRQ - 9; 7/4 invalid) 000 IRQ9 001 IRQ10 010 IRQ11 011 IRQ12 100 reserved 101 IRQ14 110 IRQ15 111 reserved 02h BYTE BIOS features bit 7: extended BIOS translation for drives >1G enabled bit 6: ??? bit 5: immediate return on seek command enabled bit 4: BIOS support for more than 2 drives enabled bit 3: dynamically scan SCSI bus for BIOS devices bit 2: system boot (INT 19h) controlled by host adapter BIOS bit 1: host adapter BIOS (configuration utility reserved BIOS space) enabled bit 0: support removable disks under BIOS as fixed disks 03h BYTE DMA transfer rate (see #9001) 04h BYTE bit 7: BIOS support for the floptical drives enabled bit 6: don't display message during BIOS initialization bits 5-4: ??? bits 3-0: bus on time 05h BYTE bit 7: ??? bits 6-0: bus off time 06h BYTE bit 7: (AHA-154xCP) somehow related to SCSI termination??? bit 6: (AHA-154xCP) somehow related to SCAM??? bit 5: ??? bits 4-3: reserved??? (0) bit 2: reset SCSI bus at power-on bit 1: host adapter SCSI termination enabled bit 0: SCSI parity checking enabled 07h 7 BYTEs ??? 0Eh 8 BYTEs SCSI ID 0-7 configuration (see #P9006) 16h 8 BYTEs reserved??? (0) 1Eh BYTE ??? (41h) 1Fh BYTE ??? (06h) SeeAlso: #P9001,#P0580 Format of AHA-154xC+ SCSI ID configuration: Offset Size Description (Table P9006) 7-5: ??? 4 ignore in BIOS scan 3 send START UNIT command 2 enable Fast SCSI 1 enable disconnection 0 enable synchronous negotation SeeAlso: #P9002 Format of AMI ID string: Offset Size Description (Table P9003) 00h 4 BYTEs ASCIZ company string ("AMI") 04h 6 BYTEs ASCIZ model string 0Ah 6 BYTEs ASCIZ series string ("48") 10h 6 BYTEs ASCIZ version string ("1.00") SeeAlso: #P0580 Format of AHA-154xCP termination setting byte: Offset Size Description (Table P9004) 7-6 detection result 00 fewer than 2 terminators 01 2 terminators 10 unable to detect 11 more than 2 terminators 5-4 ??? 3-0 ??? Note: if bits 7-6 are zero and bits 5-4 are not, ASPI4DOS.SYS complains that fewer than 2 terminators detected SeeAlso: #P0580 Format of AHA-154xB+ adapter options: Offset Size Description (Table P9005) 00h BYTE disconnect status bit N is set if target ID N is unable to disconnect? 01h BYTE (AHA-154xC) ??? Note: byte at offset 01h is the same as at offset 25h in the setup data SeeAlso: #P9004 Format of AHA-154x mailbox array: Offset Size Description (Table P0581) 00h N*4 BYTEs array of N "out" mailboxes (MBO) (see #P0582) N*4 N*4 BYTEs array of N "in" mailboxes (MBI) (see #P0584) Notes: the MBO entries are scanned by the host adapter in a round-robin fashion, i.e. the host adapter first looks into an MBO which follows the one least recently used (and wraps around if it was the last one) the MBI entries are filled in a round-robin fashion, so the CPU should check the next MBI entry after the last one that was found when a new mailbox in full (bit 0 in the interrupt flag register) interrupt; CPU should also check the next MBI entries to determine if more than one MBI is ready MBI entries are absent in case of BIOS mailboxes; in this case MBI status code is returned in the command linking ID field of the command control block (CCB) target mode CCB may be posted to the host adapter in anticipation of the SCSI command reception, with the direction bits indicating the expected transfer directiin (i.e. SEND or RECEIVE command); if a SCSI command is received by the host adapter before the CCB is prepared, it requests a CCB from the host through the MBI SeeAlso: #P0577,#P0579,#P0583,#P0585,#P0587 Format of AHA-154x mailbox-out (MBO) entry: Offset Size Description (Table P0582) 00h BYTE mailbox command/status code (see #P0583,#P0585) 01h 3 BYTEs address of the command control block (CCB) (see #P0586) physical address in big-endian format SeeAlso: #P0577,#P0581,#P0584 (Table P0583) Values for mailbox out command codes: 00h mailbox/CCB is free 01h start CCB 02h abort CCB SeeAlso: #P0577,#P0581,#P0585 Format of mailbox-in (MBI) entry: Offset Size Description (Table P0584) 00h BYTE MBI status code (see #0584) ---MBI status code 10h--- 01h BYTE initiator and LUN bits 7-5: SCSI initiator ID bit 4: RECEIVE command received bit 3: SEND command received bits 2-0: LUN 02h WORD data length 2 high bytes of the data length in SCSI SEND/RECEIVE command in big-endian format ---other MBI status codes--- 01h 3 BYTEs CCB pointer physical address in big-endian format SeeAlso: #P0582,#P0577,#P0581,#P0587 (Table P0585) Values for mailbox in status codes: 00h command in progress 01h CCB completed 02h CCB aborted 03h CCB abort failed 04h CCB completed with error SeeAlso: #P0584,#P0581,#P0583 Format of AHA-154x command control block (CCB): Offset Size Description (Table P0586) 00h BYTE CCB operation code (see #P0587) ---operation code 00h--- 01h BYTE address and control (see #P0601) 02h BYTE SCSI command length 03h BYTE request sense allocation length 00h request 14 bytes of sense data 01h disable auto-sense 02h-07h reserved 08h-FFh sense data length 04h 3 BYTEs data length in big-endian format 07h 3 BYTEs data pointer physical address in big-endian format 0Ah 3 BYTEs link pointer (link to the next CCB for the linked commands) physical address in big-endian format 0Dh BYTE command linking ID (for the linked commands) (return) MBI status code if this CCB is in a BIOS mailbox (see #P0585) 0Eh BYTE (return) host adapter status (HASTAT) (see #P0589) 0Fh BYTE (return) target device status (TARSTAT) SCSI status byte 10h 2 BYTEs reserved 12h N BYTEs SCSI command descriptor block (CDB) 12h+N M BYTEs allocated for sense data (return) sense data (if requested) ---operation code 01h--- 01h BYTE address and control bits 7-5: initiator ID bits 4-3: transfer direction 01 SEND command 10 RECEIVE command 00,11 illegal combination bits 2-0: LUN 02h BYTE SCSI command length 03h BYTE request sense allocation length 04h 3 BYTEs data length 07h 3 BYTEs data pointer 0Ah 4 BYTEs reserved 0Eh BYTE (return) host adapter status (see #P0589) 0Fh BYTE (return) target device status 10h 2 BYTEs reserved 12h N BYTEs (return) SCSI CDB 12h+N M BYTEs allocated for sense data (return) sense data (to be sent to the initiator) ---operation code 02h--- 01h BYTE address and control (see #P0601) 02h BYTE SCSI command length 03h BYTE request sense allocation length 04h 3 BYTEs data segment list length (in bytes) in big-endian format 07h 3 BYTEs data segment list pointer physical address in big-endian format 0Ah 3 BYTEs link pointer 0Dh BYTE command linking ID (return) MBI status code if this CCB is in a BIOS mailbox (see #P0585) 0Eh BYTE (return) host adapter status (see #P0589) 0Fh BYTE (return) target device status 10h 2 BYTEs reserved 12h N BYTEs SCSI CDB 12h+N M BYTEs allocated for sense data (return) sense data (if requested) ---operation code 03h--- 01h BYTE address and control (see #P0601) 02h BYTE SCSI command length 03h BYTE request sense allocation length 04h 3 BYTEs data length (return) residual length 07h 3 BYTEs data pointer 0Ah 3 BYTEs link pointer 0Dh BYTE command linking ID (return) MBI status code if this CCB is in a BIOS mailbox (see #P0585) 0Eh BYTE (return) host adapter status (see #P0589) 0Fh BYTE (return) target device status 10h 2 BYTEs reserved 12h N BYTEs SCSI CDB 12h+N M BYTEs allocated for sense data (return) sense data (if requested) ---operation code 04h--- 01h BYTE address and control (see #P0601) 02h BYTE SCSI command length 03h BYTE request sense allocation length 04h 3 BYTEs data segment list length (in bytes) (return) residual length 07h 3 BYTEs data segment list pointer 0Ah 3 BYTEs link pointer 0Dh BYTE command linking ID (return) MBI status code if this CCB is in a BIOS mailbox (see #P0583) 0Eh BYTE (return) host adapter status (see #P0589) 0Fh BYTE (return) target device status 10h 2 BYTEs reserved 12h N BYTEs SCSI CDB 12h+N M BYTEs allocated for sense data (return) sense data (if requested) ---operation code 81h--- 01h BYTE address and control bits 7-5: target ID bits 4-0: reserved Note: if a SCSI command completes with the BUSY status, the host adapter periodically restarts it until it completes with other status if a SCSI command completes with the CHECK CONDITION status, the host adapter automatically issues a REQUEST SENSE command with the data length specified by request sense allocation length field; the actual bytes returned are placed in the area allocated for sense data; but if the request sense allocation length was 01h, no REQUEST SENSE command is issued if the host adapter completes a SCSI command with the CHECK CONDITION status while it is operating in the target mode, the same sense data that will later be received by the initiator is also placed in the area allocated for sense data command linking is not supported in target mode for a target mode CCB target device status field is used to indicate to the host what status the host adapter returned to the initiator; SCSI CDB field is used to return the CDB from the initiator SeeAlso: #P0577,#P0582,#P0584 (Table P0587) Values for CCB type: 00h initiator CCB 01h target CCB (not on AHA-1540/W1542A) 02h initiator CCB with scatter/gather (see #P0590) (not on AHA-1540) 03h initiator CCB with residual length (AHA-154xB or higher) 04h initiator CCB with scatter/gather and residual length (see #P0590) (AHA-154xB or higher) 81h bus device reset CCB Note: residual length is returned in the data length field of CCB initiator CCB with scatter/gather cannot have a zero data length or contain more than 16 entries SeeAlso: #P0577,#P0586 Bitfields for the initiator mode address and control CCB field: Bit(s) Description (Table P0601) 7-5 target ID 4-3 transfer direction 00 determined by the SCSI command 01 inbound data transfer, length is checked 10 outbound data transfer, length is checked 11 no data transfer (suppress inbound data transfer) 2-0 LUN SeeAlso: #P0586,#P0589 (Table P0589) Values for host adapter status: 00h command complete 0Ah linked command complete (linked CCBs only) 0Bh linked command complete with flag (linked CCBs only) 11h selection time out 12h data overrun/underrun 13h unexpected bus free 14h target bus phase sequence failure 15h invalid mailbox out command 16h invalid CCB operation code 17h linked CCB does not have the same LUN 18h (not AHA-1540/W1542A) invalid target direction received from host (target mode) 19h (not AHA-1540/W1542A) duplicate CCB received (target mode) 1Ah invalid CCB or segment list parameter Notes: in the initiator mode, if the target attempted to transfer more data than was allocated by the data length field or the sum of the data segment length fields, and the length checking was enabled via bits 4-3 of the address and control field, the CCB will be returned with a host status of 12h; if the length checking was not enabled, command will be completed without error in the target mode, if the transfer length specified by the SEND/ RECEIVE command is not equal to that specified in the target mode CCB the host adapter will notify the CPU, setting the incorrect length indication bit (ILI), bit 5 of byte 2 in the area allocated for sense data; also, bytes 3..6 in this area will contain the residue of the length requested in the SSCI command and the data length in the CCB (MSB first); if it is negative the GOOD status will be returned to the initiator, else the CHECK CONDITION status will be returned (with subsequent REQUEST SENSE returning ILI in byte 2 and residue in bytes 3..6 of the sense data); the CCB will be returned with a host status of 12h in both cases will be completed without error in case of target bus sequence failure host adapter will generate a SCSI reset condition setting bit 3 in the interrupt flag register and generating an interrupt in target mode one CCB may be presented for each unique combination of LUN, Initiator, and direction; if a second CCB to the same LUN and initiator with the same direction bit is sent to the host adapter, the CCB will be returned with a host status of 19h if a segment list with a zero length segment or invalid segment list boundaries was received or a CCB parameter was invalid, the CCB will be returned with a host status of 1Ah SeeAlso: #P0577,#P0586,#P0601 Format of AHA-154x scatter/gather segment: Offset Size Description (Table P0590) 00h 3 BYTEs data length in big-endian format 03h 3 BYTEs data pointer physical address in big-endian format Note: if the segment ends at odd/even bondary, the next segment must begin on the same boundary SeeAlso: #P0577 ----------P0330033F-------------------------- PORT 0330-033F - CompaQ SCSI adapter. alternate address at 0130 --------d-P0330033F-------------------------- PORT 0330-033F - Philips CD-ROM player CM50 --------d-P03340337-------------------------- PORT 0334-0337 - Adaptec 154xB/154xC SCSI adapter. Range: four ports at any of 0130, 0134, 0230, 0234, 0330 (default) or 0334 --------s-P0338------------------------------ PORT 0338 - AdLib soundblaster card --------S-P0338033F-------------------------- PORT 0338-033F - COM port addresses on UniRAM card by German magazine c't Range: selectable from 0238, 02E8, 02F8, 0338, 03E0, 03E8, 03F8 ----------P0340034F-------------------------- PORT 0340-034F - Philips CD-ROM player CM50 ----------P0340034F-------------------------- PORT 0340-034F - SCSI (1st Small Computer System Interface) adapter Range: alternate address at 0140-014F --------s-P0340------------------------------ PORT 0340 - Crystal Semiconductor CDB4922 evaluation board Desc: the CDB4922 is an evaluation board for the CS4922 MPEG audio decoder (see I2C xxh"CS4922") --------s-P0340034F-------------------------- PORT 0340-034F - Gravis Ultra Sound by Advanced Gravis Range: The I/O address range is dipswitch selectable from: 0200-020F and 0300-030F 0210-021F and 0310-031F 0220-022F and 0320-032F 0230-023F and 0330-033F 0240-024F and 0340-034F 0250-025F and 0350-035F 0260-026F and 0360-036F 0270-027F and 0370-037F Note: the AMD InterWave chip provides a superset of the UltraSound's functionality, including these ports SeeAlso: PORT 0240h-024Fh,PORT 0746h 0340 -W MIDI Control (see #P0591) 0340 R- MIDI Status (see #P0592) 0341 -W MIDI Transmit Data 0341 R- MIDI Receive Data 0342 RW GF1 Page Register / Voice Select 0343 RW GF1/Global Register Select (see #P0593) 0344 RW GF1/Global Data Low Byte (16 bits) 0345 RW GF1/Global Data High Byte (8 bits) 0346 -W Mixer Data Port 0347 RW GF1 DRAM Direct Read Write at Loction pointed with regs 43 and 44 Bitfields for Gravis Ultra Sound MIDI control register: Bit(s) Description (Table P0591) 7 Receive IRQ (1 = enabled) 5-6 Xmit IRQ 0-1 Master Reset (1 = enabled) SeeAlso: #P0546,#P0548,#P0592 Bitfields for Gravis Ultra Sound MIDI status register: Bit(s) Description (Table P0592) 7 Interrupt pending 5 Overrun Error 4 Framing Error 1 Transmit Register Empty 0 Receive Register Empty SeeAlso: #P0591,#P0593 (Table P0593) Values for Gravis Ultra Sound GF1/Global Registers: ---Voice specific registers--- 00h w Voice Control (see #P0595) 01h w Frequency Control bit 15-10 Integer Portion bit 9-1 Fractional Portion 02h w Start Address HIGH bit 12-0 Address Lines 19-7 03h w Start Address LOW bit 15-9 Address Lines 6-0 bit 8-5 Fractional Part of Start Address 04h w End Address HIGH bit 12-0 Address Lines 19-7 05h w End Address LOW bit 15-9 Address Lines 6-0 bit 8-5 Fractional Part of End Address 06h w Volume Ramp Rate bit 5-0 Amount added bit 7-6 Rate 07h w Volume Ramp Start bit 7-4 Exponent bit 3-0 Mantissa 08h w Volume Ramp End bit 7-4 Exponent bit 3-0 Mantissa 09h w Current Volume bit 15-12 Exponent bit 11-4 Mantissa 0Ah w Current Address HIGH bit 12-0 Address Lines 19-7 0Bh w Current Address LOW bit 15-9 Address Lines 6-0 bit 8-0 Fractional Position 0Ch w Pan Position bit 3-0 Pan Postion 0Dh w Volume Control (see #P0596) 0Eh w Active Voices bit 5-0 #Voices -1 (allowed 13 - 31) 0Fh w IRQ Source Register (see #P0597) ---NOT voice specific--- 41h r/w DRAM DMA Control (see #P0598) 42h w DMA Start Address bits 15-0 DMA Address Lines 19-4 43h w DRAM I/O Address LOW 44h w DRAM I/O Address HIGH bits 0-3 Upper 4 Address Lines 45h r/w Timer Control bit 3 Enable Timer 2 bit 2 Enable Timer 1 46h w Timer 1 Count (granularity of 80 micro sec) 47h w Timer 2 Count (granulatity of 320 micro sec) 48h w Sampling Frequency rate = 9878400 / (16 * (FREQ + 2)) 49h r/w Sampling Control (see #P0599) 4Bh w Joystick Trim DAC 4Ch r/w RESET bit 2 GF1 Master IRQ Enable bit 1 DAC Enable bit 0 Master Reset ---Voice specific registers--- 80h r Voice Control (see 00h) 81h r Frequency Control (see 01h) 82h r Start Address HIGH (see 02h) 83h r Start Address LOW (see 03h) 84h r End Address HIGH (see 04h) 85h r End Address LOW (see 05h) 86h r Volume Ramp Rate (see 06h) 87h r Volume Ramp Start (see 07h) 88h r Volume Ramp End (see 08h) 89h r Current Volume (see 09h) 8Ah r Current Address HIGH (see 0Ah) 8Bh r Current Address LOW (see 0Bh) 8Ch r Pan Position (see 0Ch) 8Dh r Volume Control (see 0Dh) 8Eh r Active Voices (see 0Eh) 8Fh r IRQ Status (see 0Fh) SeeAlso: #P0592,#P0594 (Table P0594) Values for InterWave synthesizer registers: ---voice-specific registers--- 10h w synthesizer upper address 11h w synthesizer effects address high (16 bits) 12h w synthesizer effects address low (16 bits) 13h w synthesizer left offset (16 bits) 14h w synthesizer effects output accumulator select 15h w synthesizer mode select 16h w synthesizer effects volume (16 bits) 17h w synthesizer frequency LFO 18h w synthesizer volume LFO ---NOT voice-specific--- 19h w synthesizer global mode 1Ah w synthesizer LFO base address (16 bits) ---voice-specific registers--- 1Bh w synthesizer right offset (16 bits) 1Ch w synthesizer left offset (16 bits) 1Dh w synthesizer effect volume final (16 bits) ---NOT voice-specific--- 41h r/w local memory control: DMA control 42h r/w local memory control: DMA start address bits 19-4 (16 bits) 43h w local memory control: I/O address low (16 bits) 44h w local memory control: I/O address high (16 bits) 45h r/w AdLib/SoundBlaster control 46h r/w AdLib timer 1 47h r/w AdLib timer 2 49h r/w ADC sample control 4Bh r/w joystick trim 4Ch w GUS reset 50h r/w local memory control: DMA start address bits 23-20/3-0 (16 bits) 51h r/w local memory control: 16-bit access 52h r/w local memory control: configuration 53h r/w local memory control: control 54h r/w local memory control: record FIFO base address bits 23-8 (16-bit) 55h r/w local memory control: playback FIFO base address bits 23-8 (16-bit) 56h r/w local memory control: FIFO size (16-bit) 57h r/w local memory control: DMA interleave control (16-bit) 58h r/w local memory control: DMA interleaev base address bits 23-8 59h r/w compatibility control 5Ah r/w decode control 5Bh r/w version number 5Ch r/w MPU-401 emulation control A 5Dh r/w MPU-401 emulation control B 5Eh w MIDI receive FIFO access 5Fh - reserved 60h r/w emulation IRQ ---voice-specific registers--- 90h r synthesizer upper address 91h r synthesizer effects address high (16 bits) 92h r synthesizer effects address low (16 bits) 93h r synthesizer left offset (16 bits) 94h r synthesizer effects output accumulator select 95h r synthesizer mode select 96h r synthesizer effects volume (16 bits) 97h r synthesizer frequency LFO 98h r synthesizer volume LFO ---NOT voice-specific--- 99h r synthesizer global mode 9Ah r synthesizer LFO base address (16 bits) ---voice-specific registers--- 9Bh r synthesizer right offset (16 bits) 9Ch r synthesizer left offset (16 bits) 9Dh r synthesizer effect volume final (16 bits) ---NOT voice-specific--- 9Fh r synthesizer voices IRQ Note: these registers are *in*addition* to the Gravis UltraSound registers SeeAlso: #P0593 Bitfields for Gravis Ultra Sound voice control global register: Bit(s) Description (Table P0595) 7 IRQ pending 6 Direction 5 Enable WAVE IRQ 4 Enable bi-directional Looping 3 Enable Looping 2 Size data (8/16 bits) 1 Stop Voice 0 Voice Stopped SeeAlso: #P0593,#P0596 Bitfields for Gravis Ultra Sound volume control global register: Bit(s) Description (Table P0596) 7 IRQ Pending 6 Direction 5 Enable Volume Ramp IRQ 4 Enable bi-directional Looping 3 Enable Looping 2 Rollover Condition 1 Stop Ramp 0 Ramp Stopped SeeAlso: #P0593,#P0595 Bitfields for Gravis Ultra Sound IRQ source register: Bit(s) Description (Table P0597) 7 WaveTable IRQ pending 6 Volume Ramp IRQ pending 4-0 Voice Number SeeAlso: #P0593,#P0595,#P0598 Bitfields for Gravis Ultra Sound DRAM DMA control register: Bit(s) Description (Table P0598) 7 Invert MSB 6 Data Size (8/16 bits) 5 DMA Pending 3-4 DMA Rate Divider 2 DMA Channel Width (8/16 bits) 1 DMA Direction (1 = read) 0 DMA Enable SeeAlso: #P0593,#P0597 Bitfields for Gravis Ultra Sound sampling control register: Bit(s) Description (Table P0599) 7 Invert MSB 6 DMA IRQ pending 5 DMA IRQ enable 2 DMA width (8/16 bits) 1 Mode (mone/stereo) 0 Start Sampling SeeAlso: #P0593 ----------P03400357-------------------------- PORT 0340-0357 - RTC (1st Real Time Clock for XT) (used by TIMER.COM v1.2 which is the 'standard' timer program) Range: alternate at 0240-0257 SeeAlso: PORT 0240h-0257h 0340 RW 0.001 seconds 0-99 0341 RW 0.1 and 0.01 seconds 0-99 0342 RW seconds 0-59 0343 RW minutes 0-59 0343 RW hours 0-23 0345 RW day of week 1-7 0346 RW day of month 1-31 0347 RW month 1-12 0348 RW RAM (upper nybble only) 0349 RW year 0-99 034A RW RAM last month storage 034B RW RAM year storage (-80) 034C RW RAM reserved 034D RW RAM not used 034E RW RAM not used 034F RW RAM not used 0350 R- interrupt status register 0351 -W interrupt control register 0352 -W counter reset 0353 -W RAM reset 0354 R- status bit 0355 -W GO command 0356 ?? standby interrupt 0357 ?? test mode --------d-P0340035F-------------------------- PORT 0340-035F - Adaptec AHA-152x SCSI adapter Range: alternate address at 0140 Note: Adaptec AHA-152x SCSI adapter series are based upon Adaptec AIC-6260/6360/6370 SCSI controllers SeeAlso: PORT xxxxh"Adaptec AIC-78xx" +000 RW SCSI sequence control register (SCSISEQ) (see #P0600) +001 RW SCSI transfer control register 0 (SXFRCTL0) (see #P0601) +002 RW SCSI transfer control register 1 (SXFRCTL1) (see #P0602) +003 R- SCSI control signal read register (SCSISIGI) (see #P0603) +003 -W SCSI control signal write register (SCSISIGO) (see #P0604) +004 RW SCSI rate control register (SCSIRATE) (see #P0605) +005 RW SCSI ID register (SCSIID) (see #P0606) +006 RW SCSI latched data register (SCSIDAT) read/write causes -ACK to pulse +007 R? SCSI data bus register (SCSIBUS) +008 RW SCSI transfer count register (STCNT) (3 bytes long) +00B R- SCSI status register 0 (SSTAT0) (see #P0607) +00B -W clear SCSI interrupt register 0 (CLRSINT0) (see #P0608) +00C R- SCSI status register 1 (SSTAT1) (see #P0609) +00C -W clear SCSI interrupt register 1 (CLRSINT1) (see #P0610) +00D R- SCSI status register 2 (SSTAT2) (see #P0611) +00E R- SCSI status register 3 (SSTAT3) (see #P0612) +00E ?W SCSI test control register (SCSITEST) (see #P0613) +00F R- SCSI status register 4 (SSTAT4) (see #P0614) +00F -W clear SCSI interrupt register 4 (CLRSINT4) (see #P0615) +010 RW SCSI interrupt mode register 0 (SIMODE0) (see #P0616) +011 RW SCSI interrupt mode register 1 (SIMODE1) (see #P0617) +012 RW DMA control register 0 (DMACNTRL0) (see #P0618) +013 RW DMA control register 1 (DMACNTRL1) (see #P0619) +014 RW DMA status register (DMASTAT) (see #P0620) +015 RW FIFO status register (FIFOSTAT) +016w RW data port register (DATAPORT) +018 RW burst control register (BRSTCNTRL) (see #P0621) +01A RW port A register (PORTA) (see #P0622) +01B RW port B register (PORTB) (see #P0623) +01C RW revision register (REV) +01D RW stack register (STACK) +01E RW test register (TEST) (see #P0624) +01F R? (AIC-6360+) ID register (ID) 32-byte ID string can be read here Notes: the SCSI latched data register is used to transfer data on the SCSI bus during automatic or manual PIO mode the SCSI data bus register reflects the state of SCSI data bus lines directly Bitfields for SCSI sequence control register (SCSISEQ): Bit(s) Description (Table P0600) 7 enable target mode (TEMODEO) 6 enable selection out (ENSELO) 5 enable selection in (ENSELI) 4 enable reselection in (ENRESELI) 3 "ENAUTOATNO" 2 "ENAUTOATNI" 1 enable auto -ATN on parity error (ENAUTOATNP) 0 SCSI reset out (SCSIRSTO) Note: each bit when set starts a specific SCSI sequence on the bus SeeAlso: #P0602,#P0607,#P0608,#P0616 Bitfields for SCSI transfer control register 0 (SXFRCTL0): Bit(s) Description (Table P0601) 7 SCSI FIFO enable (SCSIEN) 6 DMA FIFO enable (DMAEN) 5 channel enable (CHEN) 4 clear SCSI transfer counter (CLRSTCNT) 3 SCSI PIO enable (SPIOEN) 2 SCAM enable (SCAMEN) 1 clear channel (CLRCH) 0 reserved SeeAlso: #P0602,#P0607,#P0611,#P0618,#P0620 Bitfields for SCSI transfer control register 1 (SXFRCTL1): Bit(s) Description (Table P0602) 7 bit bucket (BITBUCKET) 6 SCSI counter wrap enable (SWRAPEN) 5 enable SCSI parity check (ENSPCHK) 4-3 selection time-out select (STIMESEL) 00 256 ms 01 128 ms 10 64 ms 11 32 ms 2 enable selection timer (ENSTIMER) 1 byte align (BYTEALIGN) 0 reserved SeeAlso: #P0600,#P0601 Bitfields for SCSI control signal read register (SCSISIGI): Bit(s) Description (Table P0603) 7 -C/D input (CDI) 6 -I/O input (IOI) 5 -MSG input (MSGI) 4 -ATN input (ATNI) 3 -SEL input (SELI) 2 -BSY input (BSYI) 1 -REQ input (REQI) 0 -ACK input (ACKI) Note: this register reflects the actual state of the SCSI bus control lines SeeAlso: #P0604 Bitfields for SCSI control signal write register (SCSISIGO): Bit(s) Description (Table P0604) 7 -C/D output (CDO) 6 -I/O output (IOO) 5 -MSG output (MSGO) 4 -ATN output (ATNO) 3 -SEL output (SELO) 2 -BSY output (BSYO) 1 -REQ output (REQO) 0 -ACK output (ACKO) Notes: writing to this register modifies the control signals on the bus; only those signals that are allowed in the current mode (initiator/target) are asserted bits 7-5 in initiator mode represent the expected SCSI bus phase and can be used to trigger phase mismatch and phase change interrupts SeeAlso: #P0603 Bitfields for SCSI rate control register (SCSIRATE): Bit(s) Description (Table P0605) 7 reserved 6-4 synchronous transfer rate (SXFR) rate = 100 + SXFR * 25 (ns) 3-0 synchronous offset (SOFS) Note: contents of this register determine the synchronous SCSI data transfer rate and the maximum synchronous -REQ/-ACK offset; an offset of 0 in the bits 3-0 disables synchronous data transfers, any offset value greater than 0 enables snchronous transfers SeeAlso: #P0611 Bitfields for SCSI ID register (SCSIID): Bit(s) Description (Table P0606) 7 reserved 6-4 our ID (OID) 3 reserved 2-0 target ID (TID) Note: this register contains the SCSI ID of the board and the current target on the selected channel SeeAlso: #P0982 Bitfields for SCSI status register 0 (SSTAT0): Bit(s) Description (Table P0607) 7 target mode (TARGET) 6 selection out done (SELDO) 5 selection in done (SELDI) 4 selection in progress (SELINGO) 3 SCSI counter wrap (SWRAP) 2 SCSI PIO done (SDONE) 1 SCSI PIO ready (SPIORDY) 0 DMA done (DMADONE) Note: bits 1-0 and 6-4 are self-clearing bit 2 is set when the SCSI transfer count register decrements to 0 SeeAlso: #P0600,#P0601,#P0608,#P0616 Bitfields for clear SCSI interrupt register 0 (CLRSINT0): Bit(s) Description (Table P0608) 7 set SCSI PIO done? (SETSDONE) 6 clear selection out done (CLRSELDO) 5 clear selection in done (CLRSELDI) 4 clear selection in progress (CLRSELINGO) 3 clear SCSI counter wrap (CLRSWRAP) 2 clear SCSI PIO done (CLRSDONE) 1 clear SCSI PIO ready (CLRSPIORDY) 0 reserved Note: writing 1 to