PORTS LIST Release 61 Last change 16jul00 Copyright (c) 1989-1999,2000 Ralf Brown [This file originally by Wim Osterholt , though it has grown considerably since.] XT, AT and PS/2 I/O port addresses Do NOT consider this information to be complete and accurate. If you want to do hardware programming ALWAYS check the appropriate data sheets (but even they are sometimes in error!). Be aware that erroneous port programming can put your data or even your hardware at risk. There are a number of memory-mapped addresses in use for I/O; see MEMORY.LST for details on memory-mapped I/O. --------!---Note----------------------------- Note: the port description format is: PPPPw RW description where: PPPP is the four-digit hex port number or a plus sign and three hex digits to indicate an offset from a base port address w is blank for byte-size port, 'w' for word, and 'd' for dword R is dash (or blank) if not readable, 'r' if sometimes readable, 'R' if "always" readable, '?' if readability unknown W is dash (or blank) if not writable, 'w' if sometimes writable, 'W' if "always" writable, 'C' if write-clear, and '?' if writability unknown ----------P0000001F-------------------------- PORT 0000-001F - DMA 1 - FIRST DIRECT MEMORY ACCESS CONTROLLER (8237) SeeAlso: PORT 0080h-008Fh"DMA",PORT 00C0h-00DFh 0000 R- DMA channel 0 current address byte 0, then byte 1 0000 -W DMA channel 0 base address byte 0, then byte 1 0001 RW DMA channel 0 word count byte 0, then byte 1 0002 R- DMA channel 1 current address byte 0, then byte 1 0002 -W DMA channel 1 base address byte 0, then byte 1 0003 RW DMA channel 1 word count byte 0, then byte 1 0004 R- DMA channel 2 current address byte 0, then byte 1 0004 -W DMA channel 2 base address byte 0, then byte 1 0005 RW DMA channel 2 word count byte 0, then byte 1 0006 R- DMA channel 3 current address byte 0, then byte 1 0006 -W DMA channel 3 base address byte 0, then byte 1 0007 RW DMA channel 3 word count byte 0, then byte 1 0008 R- DMA channel 0-3 status register (see #P0001) 0008 -W DMA channel 0-3 command register (see #P0002) 0009 -W DMA channel 0-3 write request register (see #P0003) 000A RW DMA channel 0-3 mask register (see #P0004) 000B -W DMA channel 0-3 mode register (see #P0005) 000C -W DMA channel 0-3 clear byte pointer flip-flop register any write clears LSB/MSB flip-flop of address and counter registers 000D R- DMA channel 0-3 temporary register 000D -W DMA channel 0-3 master clear register any write causes reset of 8237 000E -W DMA channel 0-3 clear mask register any write clears masks for all channels 000F rW DMA channel 0-3 write mask register (see #P0006) Notes: the temporary register is used as holding register in memory-to-memory DMA transfers; it holds the last transferred byte channel 2 is used by the floppy disk controller on the IBM PC/XT channel 0 was used for the memory refresh and channel 3 was used by the hard disk controller on AT and later machines with two DMA controllers, channel 4 is used as a cascade for channels 0-3 command and request registers do not exist on a PS/2 DMA controller Bitfields for DMA channel 0-3 status register: Bit(s) Description (Table P0001) 7 channel 3 request active 6 channel 2 request active 5 channel 1 request active 4 channel 0 request active 3 channel terminal count on channel 3 2 channel terminal count on channel 2 1 channel terminal count on channel 1 0 channel terminal count on channel 0 SeeAlso: #P0002,#P0481 Bitfields for DMA channel 0-3 command register: Bit(s) Description (Table P0002) 7 DACK sense active high 6 DREQ sense active high 5 =1 extended write selection =0 late write selection 4 rotating priority instead of fixed priority 3 compressed timing (two clocks instead of four per transfer) =1 normal timing (default) =0 compressed timing 2 =1 enable controller =0 enable memory-to-memory 1-0 channel number SeeAlso: #P0001,#P0004,#P0005,#P0482 Bitfields for DMA channel 0-3 request register: Bit(s) Description (Table P0003) 7-3 reserved (0) 2 =0 clear request bit =1 set request bit 1-0 channel number 00 channel 0 select 01 channel 1 select 10 channel 2 select 11 channel 3 select SeeAlso: #P0004 Bitfields for DMA channel 0-3 mask register: Bit(s) Description (Table P0004) 7-3 reserved (0) 2 =0 clear mask bit =1 set mask bit 1-0 channel number 00 channel 0 select 01 channel 1 select 10 channel 2 select 11 channel 3 select SeeAlso: #P0001,#P0002,#P0003,#P0484 Bitfields for DMA channel 0-3 mode register: Bit(s) Description (Table P0005) 7-6 transfer mode 00 demand mode 01 single mode 10 block mode 11 cascade mode 5 direction =0 increment address after each transfer =1 decrement address 3-2 operation 00 verify operation 01 write to memory 10 read from memory 11 reserved 1-0 channel number 00 channel 0 select 01 channel 1 select 10 channel 2 select 11 channel 3 select SeeAlso: #P0002,#P0485 Bitfields for DMA channel 0-3 write mask register: Bit(s) Description (Table P0006) 7-4 reserved 3 channel 3 mask bit 2 channel 2 mask bit 1 channel 1 mask bit 0 channel 0 mask bit Note: each mask bit is automatically set when the corresponding channel reaches terminal count or an extenal EOP sigmal is received SeeAlso: #P0004,#P0486 ----------P0010001F-------------------------- PORT 0010-001F - DMA CONTROLLER (8237) ON PS/2 MODEL 60 & 80 SeeAlso: PORT 0000h-001Fh,PORT 0080h-008Fh"DMA",PORT 00C0h-00DFh 0018 -W extended function register (see #P0007) 001A -W extended function execute register Bitfields for DMA extended function register: Bit(s) Description (Table P0007) 7-4 function code (see #P0008) 3 reserved (0) 2-0 channel number 000 channel 0 select 001 channel 1 select 010 channel 2 select 011 channel 3 select 100 channel 4 select 101 channel 5 select 110 channel 6 select 111 channel 7 select (Table P0008) Values for DMA extended function codes (data go to/from PORT 001Ah): Value Description Parameters Results 00h current address register - CA0,CA1 02h write address - A0,A1,P 03h read address A0,A1,P - 04h write word count register C0,C1 - 05h read word count register - C0,C1 06h read status register - S 07h mode register - M 09h mask channel - - 0Ah unmask channel - - 0Dh master clear - - Note: CA0/CA1 LSB/MSB of the current address register A0/A1 LSB/MSB of the base address register P DMA page address C0/C1 LSB/MSB of the word count register S status register value (see #P0001, #P0481) M mode register value (see #P0005, #P0485) first, the extended function register is written, then the extended function register execute register is read/written if the function being executing requires Bitfields for DMA extended mode register: Bit(s) Description (Table P0009) 7 reserved (0) 6 =0 8-bit transfer =1 16-bit transfer 5-4 reserved (0) 3 transfer type =0 read from memory =1 write to memory 2 =0 disable memory write =1 enable memory write 1 reserved (0) 0 address select =0 use 0 as base address =1 use a value from base address register Note: the IBM PS/2 model 80 technical reference doesn't seem to mention this register's address ----------P0020003F-------------------------- PORT 0020-003F - PIC 1 - PROGRAMMABLE INTERRUPT CONTROLLER (8259A) SeeAlso: PORT 00A0h-00AFh"PIC 2",INT 08"IRQ0",INT 0F"IRQ7" 0020 -W PIC initialization command word ICW1 (see #P0010) 0020 -W PIC output control word OCW2 (see #P0015) 0020 -W PIC output control word OCW3 (see #P0016) 0020 R- PIC interrupt request/in-service registers after OCW3 request register: bit 7-0 = 0 no active request for the corresponding int. line = 1 active request for corresponding interrupt line in-service register: bit 7-0 = 0 corresponding line not currently being serviced = 1 corresponding int. line currently being serviced 0021 -W PIC ICW2,ICW3,ICW4 immed after ICW1 to 0020 (see #P0011,#P0012,#P0013) 0021 RW PIC master interrupt mask register OCW1 (see #P0014) Bitfields for PIC initialization command word ICW1: Bit(s) Description (Table P0010) 7-5 0 (only used in 8080/8085 mode) 4 ICW1 is being issued 3 (LTIM) =0 edge triggered mode =1 level triggered mode 2 interrupt vector size =0 successive interrupt vectors use 8 bytes (8080/8085) =1 successive interrupt vectors use 4 bytes (80x86) 1 (SNGL) =0 cascade mode =1 single mode, no ICW3 needed 0 ICW4 needed SeeAlso: #P0011,#P0012,#P0013 Bitfields for PIC initialization command word ICW2: Bit(s) Description (Table P0011) 7-3 address lines A0-A3 of base vector address for PIC 2-0 reserved SeeAlso: #P0010,#P0012,#P0013 Bitfields for PIC initialization command word ICW3: Bit(s) Description (Table P0012) 7-0 =0 slave controller not attached to corresponding interrupt pin =1 slave controller attached to corresponding interrupt pin SeeAlso: #P0010,#P0011,#P0013 Bitfields for PIC initialization command word ICW4: Bit(s) Description (Table P0013) 7-5 reserved (0) 4 running in special fully-nested mode 3-2 mode 0x nonbuffered mode 10 buffered mode/slave 11 buffered mode/master 1 Auto EOI 0 =0 8085 mode =1 8086/8088 mode SeeAlso: #P0010,#P0011,#P0012 Bitfields for PIC output control word OCW1: Bit(s) Description (Table P0014) 7 disable IRQ7 (parallel printer interrupt) 6 disable IRQ6 (diskette interrupt) 5 disable IRQ5 (fixed disk interrupt) 4 disable IRQ4 (serial port 1 interrupt) 3 disable IRQ3 (serial port 2 interrupt) 2 disable IRQ2 (video interrupt) 1 disable IRQ1 (keyboard, mouse, RTC interrupt) 0 disable IRQ0 (timer interrupt) SeeAlso: #P0015,#P0016,#P0418 Bitfields for PIC output control word OCW2: Bit(s) Description (Table P0015) 7-5 operation 000 rotate in auto EOI mode (clear) 001 (WORD_A) nonspecific EOI 010 (WORD_H) no operation 011 (WORD_B) specific EOI 100 (WORD_F) rotate in auto EOI mode (set) 101 (WORD_C) rotate on nonspecific EOI command 110 (WORD_E) set priority command 111 (WORD_D) rotate on specific EOI command 4-3 reserved (00 - signals OCW2) 2-0 interrupt request to which the command applies (only used by WORD_B, WORD_D, and WORD_E) SeeAlso: #P0014,#P0016 Bitfields for PIC output control word OCW3: Bit(s) Description (Table P0016) 7 reserved (0) 6-5 special mask 0x no operation 10 reset special mask 11 set special mask mode 4-3 reserved (01 - signals OCW3) 2 poll command 1-0 function 0x no operation 10 read interrupt request register on next read from PORT 0020h 11 read interrupt in-service register on next read from PORT 0020h Note: the special mask mode permits all other interrupts (even those with lower priority) to be processed while an interrupt is already in service, but will not re-issue an interrupt for a particular IRQ while it remains in service SeeAlso: #P0014,#P0015 ----------P0022------------------------------ PORT 0022 - Intel 82439TX Chipset - Power Control register SeeAlso: PORT 0022h"82443BX" 0022 RW PM2 Register Block bits 7-1: reserved bit 0: Arbiter Disable --------p-P0022------------------------------ PORT 0022 - Intel 82443BX - "PM2_CTL" ACPI Power Control 2 Register SeeAlso: PORT 0022h"82439TX",#01142 at INT 1A/AX=B10Ah/SF=8086h 0022 RW ACPI Power Control Register 2 bits 7-1: reserved bit 0: disable primary PCI and AGP arbiter requests ----------P00220023-------------------------- PORT 0022-0023 - CHIP SET DATA Note: These two ports are used by numerous chipsets. Various chipsets are detailed below. 0022 -W index for accesses to data port 0023 RW chip set data ----------P00220023-------------------------- PORT 0022-0023 - Cyrix Cx486SLC/DLC PROCESSOR - CACHE CONFIGURATION REGISTERS SeeAlso: PORT 0022h"5x86",PORT 0022h"6x86" 0022 -W index for accesses to next port (see #P0017) 0023 RW cache configuration register array (indexed by PORT 0022h) Note: the index must be written to PORT 0022h before every access to PORT 0023h; out-of-sequence accesses or index values not supported by the processor generate external I/O cycles (Table P0017) Values for Cyrix Cx486SLC/DLC Cache Configuration register number: C0h CR0 (see #P0019) C1h CR1 (see #P0020) C4h non-cacheable region 1, start address bits 31-24 C5h non-cacheable region 1, start address bits 23-16 C6h non-cacheable region 1, start addr 15-12, size (low nibble) (see #P0018) C7h non-cacheable region 2, start address bits 31-24 C8h non-cacheable region 2, start address bits 23-16 C9h non-cacheable region 2, start addr 15-12, size (low nibble) (see #P0018) CAh non-cacheable region 3, start address bits 31-24 CBh non-cacheable region 3, start address bits 23-16 CCh non-cacheable region 3, start addr 15-12, size (low nibble) (see #P0018) CDh non-cacheable region 4, start address bits 31-24 CEh non-cacheable region 4, start address bits 23-16 CFh non-cacheable region 4, start addr 15-12, size (low nibble) (see #P0018) SeeAlso: #P0023,#P0021 (Table P0018) Values for Cyrix Cx486SLC/DLC non-cacheable region sizes: 00h disabled 01h 4K 02h 8K 03h 16K 04h 32K 05h 64K 06h 128K 07h 256K 08h 512K 09h 1M 0Ah 2M 0Bh 4M 0Ch 8M 0Dh 16M 0Eh 32M 0Fh 4G SeeAlso: #P0017 Bitfields for Cyrix Cx486SLC/DLC Configuration Register 0: Bit(s) Description (Table P0019) 0 "NC0" first 64K of each 1M noncacheable in real/V86 1 "NC1" 640K-1M noncacheable 2 "A20M" enables A20M# input pin 3 "KEN" enables KEN# input pin 4 "FLUSH" enables FLUSH input pin 5 "BARB" enables internal cache flushing on bus holds 6 "C0" cache direct-mapped instead of 2-way associative 7 "SUSPEND" enables SUSP# input and SUSPA# output pins SeeAlso: #P0017,#P0020,#P0032 Bitfields for Cyrix Cx486SLC/DLC Configuration Register 1: Bit(s) Description (Table P0020) 0 "RPL" enables output pins RPLSET and RPLVAL# SeeAlso: #P0017,#P0019,#P0024 ----------P00220023-------------------------- PORT 0022-0023 - Cyrix 486S2/D2/DX/DX2/DX4 PROCESSOR - CONFIGURATION REGISTERS SeeAlso: PORT 0022h"Cx486SLC",PORT 0022h"5x86",PORT 0022h"6x86" 0022 -W index for accesses to next port (see #P0021) 0023 RW cache configuration register array (indexed by PORT 0022h) Note: the index must be written to PORT 0022h before every access to PORT 0023h; out-of-sequence accesses or index values not supported by the processor generate external I/O cycles (Table P0021) Values for Cyrix 486S2/D2/DX/DX2/DX4 configuration register number: C2h CR2 (see #P0025) C3h CR3 (see #P0026) CDh SMM region, start address bits 31-24 CEh SMM region, start address bits 23-16 CFh SMM region, start addr 15-12, size (low nibble) (see #P0018) FEh R Device Identification #0 (see #P0022) CPU device ID FFh R Device Identification #1 bits 3-0: revision bits 7-4: stepping SeeAlso: #P0017,#P0023,#P0031 (Table P0022) Values for Cyrix device identification: (#0 /#1) 00h Cx486SLC 01h Cx486DlC 02h Cx486SLC2 03h Cx486DLC2 04h Cx486SRx 05h Cx486DRx 06h Cx486SRx2 07h Cx486DRx2 10h Cx486S (B-step) 11h Cx486S2 (B-step) 12h Cx486Se (B-step) 13h Cx486S2e (B-step) 1Ah/05h Cx486DX-40 1Bh/08h Cx486DX2-50 1Bh/0Bh Cx486DX2-66 1Bh/31h Cx486DX2-v80 1Fh/36h Cx486DX4-v100 28h 5x86 1xs 29h 5x86 2xs 2Ah 5x86 1xp 2Bh 5x86 2xp 2Ch 5x86 4xs 2Dh 5x86 3xs 2Eh 5x86 4xp 2Fh 5x86 3xp 30h 6x86 1xs 31h 6x86 2xs 32h 6x86 1xp 33h 6x86 2xp 34h 6x86 4xs 35h 6x86 3xs 36h 6x86 4xp 37h 6x86 3xp Note: #0 is the value in configuration register FEh, while #1 is the value in configuration register FFh SeeAlso: #P0021 ----------P00220023-------------------------- PORT 0022-0023 - Cyrix 5x86 PROCESSOR - CONFIGURATION CONTROL REGISTERS SeeAlso: PORT 0022h"Cx486SLC",PORT 0022h"486S2",PORT 0022h"6x86" 0022 -W index for accesses to next port (see #P0023) 0023 RW configuration control register array (indexed by PORT 0022h) Note: the index must be written to PORT 0022h before every access to PORT 0023h; out-of-sequence accesses or index values not supported by the processor generate external I/O cycles (Table P0023) Values for Cyrix 5x86 configuration registers: 20h Performance Control (see #P0028) C1h Configuration Control #1 (CCR1) (see #P0024) C2h Configuration Control #2 (CCR2) (see #P0025) C3h Configuration Control #3 (CCR3) (see #P0026) CDh System Memory Management address region #0 (smar0) (see #P0029) CEh System Memory Management address region #1 (smar1) CFh System Memory Management address region #2 (smar2) E8h Configuration Control Register 4 F0h Power Management (see #P0030) FEh R Device Identification #0 (see #P0022) CPU device ID FFh R Device Identification #1 bits 3-0: revision bits 7-4: stepping SeeAlso: #P0017,#P0021,#P0031 Bitfields for Cyrix 5x86,6x86 Configuration Control Register 1 (CCR1): Bit(s) Description (Table P0024) 0 reserved 1 enable SMM pins 2 system management memory access 3 main memory access 4 (6x86) no LOCK during bus cycles 6-5 reserved 7 (6x86) use address region 3 as SMM space Note: bits 1,2,7 may only be written when CCR3 bit 0 is enabled SeeAlso: #P0020,#P0025,#P0026,#P0027 Bitfields for Cyrix 5x86,6x86 Configuration Control Register 2 (CCR2): Bit(s) Description (Table P0025) 0 reserved 1 enable write-back cache interface pins 2 lock NW bit 3 suspend on HLT instruction 4 write-through region 1 5 reserved 6 enable burst write cycles 7 enable suspend pins SeeAlso: #P0024,#P0026,#P0027 Bitfields for Cyrix 5x86,6x86 Configuration Control Register 3 (CCR3): Bit(s) Description (Table P0026) 0 SMM register lock (can only be cleared in SMM mode or by CPU reset) 1 NMI enable 2 linear address burst cycles (5x86,6x86 only) =0 Pentium-compatible =1 linear sequencing 3 SMM mode (5x86 only) =0 486SL =1 Cyrix 7-4 map enable (5x86,6x86 only) 0000 only allow access to configuration registers C0h-CFh,FEh,FFh 0001 enable access to all configuration registers SeeAlso: #P0024,#P0025,#P0027,#P0028,#P0030 Bitfields for Cyrix 5x86,6x86 Configuration Control Register 4 (CCR4): Bit(s) Description (Table P0027) 2-0 I/O recovery time (000 = none, else 2^N clocks) 3 enable memory-read bypassing (5x86 only) 4 enable directory table entry cache 6-5 reserved 7 enable CPUID instruction (stepping 1+ and Cx6x86) Note: this register is only accessible when bits 7-4 of CCR3 are 0001 SeeAlso: #P0024,#P0025,#P0026 Bitfields for Cyrix 5x86 Performance Control register: Bit(s) Description (Table P0028) 0 return stack enabled (speculatively execute code after current CALL) 1 branch-target buffer enabled 2 loop enable 6-3 reserved (0) 7 load-store serialization enabled (memory reads and writes may be reorganized into optimum order) Note: this register is only accessible when bits 7-4 of CCR3 are 0001 SeeAlso: #P0030,#P0024 Bitfields for Cyrix 5x86 SMM Address Region register: Bit(s) Description (Table P0029) 3-0 block size 23-4 starting address Bitfields for Cyrix 5x86 Power Management register: Bit(s) Description (Table P0030) 1-0 core clock to bus clock ratio 00 1:1 01 2:1 10 reserved 11 3:1 2 CPU running at half bus speed, ignore bits 1-0 Note: this register is only accessible when bits 7-4 of CCR3 are 0001 ----------P00220023-------------------------- PORT 0022-0023 - Cyrix 6x86 PROCESSOR - CONFIGURATION CONTROL REGISTERS SeeAlso: PORT 0022h"Cx486",PORT 0022h"5x86" 0022 -W index for accesses to next port (see #P0023) 0023 RW configuration control register array (indexed by PORT 0022h) Note: the index must be written to PORT 0022h before every access to PORT 0023h; out-of-sequence accesses or index values not supported by the processor generate external I/O cycles (Table P0031) Values for Cyrix 6x86 configuration registers: C0h Configuration Control Register 0 (CCR0) (see #P0032) C1h Configuration Control #1 (CCR1) (see #P0024) C2h Configuration Control #2 (CCR2) (see #P0025) C3h Configuration Control #3 (CCR3) (see #P0026) C4h Address region 0 (bits 31-24) C5h Address region 0 (bits 23-16) C6h Address region 0 (bits 15-12 and size) C7h Address region 1 (bits 31-24) C8h Address region 1 (bits 23-16) C9h Address region 1 (bits 15-12 and size) CAh Address region 2 (bits 31-24) CBh Address region 2 (bits 23-16) CCh Address region 2 (bits 15-12 and size) CDh Address region 3 (bits 31-24) CEh Address region 3 (bits 23-16) CFh Address region 3 (bits 15-12 and size) D0h Address region 4 (bits 31-24) D1h Address region 4 (bits 23-16) D2h Address region 4 (bits 15-12 and size) D3h Address region 5 (bits 31-24) D4h Address region 5 (bits 23-16) D5h Address region 5 (bits 15-12 and size) D6h Address region 6 (bits 31-24) D7h Address region 6 (bits 23-16) D8h Address region 6 (bits 15-12 and size) D9h Address region 7 (bits 31-24) DAh Address region 7 (bits 23-16) DBh Address region 7 (bits 15-12 and size) DCh Region Control 0 DDh Region Control 1 DEh Region Control 2 DFh Region Control 3 E0h Region Control 4 E1h Region Control 5 E2h Region Control 6 E3h Region Control 7 E8h Configuration Control Register 4 (see #P0027) E9h Configuration Control Register 5 (see #P0033) FEh R Device Identification #0 (see #P0022) CPU device ID FFh R Device Identification #1 bits 3-0: revision bits 7-4: stepping SeeAlso: #P0017,#P0023 Bitfields for Cyrix 6x86 Configuration Control Register 0: Bit(s) Description (Table P0032) 7-2 ??? 1 address region 640K-1M is noncacheable 0 ??? SeeAlso: #P0019 Bitfields for Cyrix 6x86 Configuration Control Register 5: Bit(s) Description (Table P0033) 7-6 reserved 5 enable all address-region registers (control registers C4h-DBh) 4 assert LBA# pin on all accesses to 640K-1M 3-1 reserved 0 allocate new cache lines only on read misses SeeAlso: #P0032,#P0027,#P0031 ----------P00220023-------------------------- PORT 0022-0023 - GoldStar 286 - CHIP SET CONFIGURATION REGISTERS SeeAlso: PORT 0022h"Cx486SLC",PORT 0022h"486S2",PORT 0022h"6x86" 0022 -W index for accesses to next port (see #P0034) 0023 RW configuration control register array (indexed by PORT 0022h) (Table P0034) Values for GoldStar 286 chipset configuration register index: 60h turbo control write 00h to PORT 0023h to turn on turbo, 10h to turn it off --------X-P00220023-------------------------- PORT 0022-0023 - Intel 82358DT 'Mongoose' EISA CHIPSET - 82359 DRAM CONTROLLER Notes: this chip uses a chip ID of 01 the LIM register herein use a chip ID of 1A Index: Intel 82351 0022 -W index for accesses to data port (see #P0036,#P0037,#P0038) 0023 RW chip set data (Table P0035) Values for Intel 82351/82359 chip ID: 01h 82359 DRAM controller, general registers 02h 82351 EISA local I/O support A1h 82359 DRAM controller, EMS registers FFh no chip accessible (default) SeeAlso: #P0036,#P0037,#P0038 (Table P0036) Values for 82359 DRAM controller general register index: 00h DRAM bank 0 type bit 7 unknown bit 6-4 000 DRAM in bank 0 (standard) 001 bank 1 010 bank 2 011 bank 3 100 banks 0,1 101 banks 2,3 110 banks 0,1,2,3 111 empty (standard for 1,2,3) bit 3-2 unknown bit 1-0 00 64K chips used 01 256K 10 1M 11 4M 01h DRAM bank 1 type 02h DRAM bank 2 type 03h DRAM bank 3 type 04h DRAM speed detection/selection 05h DRAM interleave control 06h RAS line mode 07h cache-enable selection 08h mode register A (DRAM, cache) 09h mode register B (cache, burst modes, BIOS size) 0Ah mode register C (concurrency control, burst/cycle speed) 10h host timing 11h host-system delay timing 12h system timing 13h DRAM row precharge time 14h DRAM row timing 15h DRAM column timing 16h CAS pulse width 17h CAS-to-MDS delay 21h chip ID register -- selects which chip responds on these ports (see #P0035) 28h-2Ch parity-error trap address 30h page hit cycle length (read) 31h page miss cycle length (read) 32h row miss cycle length (read) 33h page hit cycle length (write) 34h page miss cycle length (write) 35h row miss cycle length (write) 40h memory enable 00000h-7FFFFh 41h memory enable 80000h-9FFFFh 42h memory enable A0000h-AFFFFh 43h memory enable B0000h-BFFFFh 44h memory enable C0000h-CFFFFh 45h memory enable D0000h-DFFFFh 46h memory enable E0000h-EFFFFh 47h memory enable F0000h-FFFFFh 4Eh remap 80000h-FFFFFh to extended memory 50h-53h programmable attribute map 1 54h-57h programmable attribute map 2 58h-5Bh programmable attribute map 3 5Ch-5Fh programmable attribute map 4 83h-84h split address register (address bits A31-A20) 85h cache control 8Bh system throttle 8Ch host throttle 8Dh host memory throttle watchdog 8Eh host system throttle 8Fh host system throttle watchdog 90h RAM enable 91h RAM disable 92h-93h elapsed-time registers 94h-95h host memory ownership request 96h-97h system memory ownership request 98h-99h host memory ownership 9Ah-9Bh system bus ownership 9Ch-9Dh host system bus request 9Eh-9Fh memory ownership transfer SeeAlso: #P0037,#P0038 (Table P0037) Values for Intel 82359 DRAM controller EMS register index: 00h EMS cotnrol 21h chip ID register -- selects which chip responds on these ports (see #P0035) 80h-8Fh EMS page registers, pages 0-7 SeeAlso: #P0036,#P0038 (Table P0038) Values for Intel 82351 EISA Local I/O register index: 21h chip ID register -- selects which chip responds on these ports (see #P0035) C0h peripheral enable register A C1h peripheral enable register B C2h parallel configuration register C3h serial configuration register A C4h floppy disk controller configuration register C5h serial configuration register B C6h COM3 port address (low) C7h COM3 port address (high) C8h COM4 port address (low) C9h COM4 port address (high) D0h-D3h general chip select lines 0-3 (mask registers) D4h-D7h general chip select line addresses 0-3 (low bytes) D8h-DBh general chip select line addresses 0-3 (high bytes) DCh extended CMOS RAM page port address (low) DDh extended CMOS RAM page port address (high) DFh extended CMOS RAM access select address (high byte) E8h-EBh EISA ID configuration registers (reflect at PORT 0C80h) SeeAlso: #P0036,#P0037 --------X-P00220023-------------------------- PORT 0022-0023 - Intel 82374EB/SB EISA CHIPSET Index: Intel 82374EB;Intel 82374SB 0022 -W index for accesses to data port (see #P0039) 0023 RW chip set data !!!29047604.pdf pg. 36 (Table P0039) Values for Intel 82374 register index: 02h ESC identification register (82374 will only respond to ports 0022h and 0023h after an 0Fh is written to this register) 08h revision ID register 40h mode select (see #P0040) 42h BIOS Chip Select A (see #P0041) 43h BIOS Chip Select B (see #P0042) 4Dh EISA clock divisor (see #P0043) 4Eh peripheral Chip Select A (see #P0044) 4Fh peripheral Chip Select B (see #P0045) 50h-53h EISA ID registers 57h scatter/gather relocate base address (see also #01075) (specifies bits 15-0 if S/G port addresses [low byte always 10h-3Fh]) 59h APIC base address relocation 60h-63h PCI IRQn# route control (see also #01076) 64h general-purpose chip select low address 0 65h general-purpose chip select high address 0 66h general-purpose chip select mask register 0 68h general-purpose chip select low address 1 69h general-purpose chip select high address 1 6Ah general-purpose chip select mask register 1 6Ch general-purpose chip select low address 2 6Dh general-purpose chip select high address 2 6Eh general-purpose chip select mask register 2 6Fh general-purpose peripheral X-Bus control ---SB only--- 70h PCI/APIC control (see #P0046) 88h test control A0h SMI control (see #P0047) A2h-A3h SMI enable (see #P0048) A4h-A7h System Event Enable (see #P0049) A8h Fast-Off timer AAh-ABh SMI Request (see #P0050) ACh Clock Scale STPCLK# low timer AEh Clock Scale STPCLK# high timer Bitfields for 82374EB mode select (register 40h): Bit(s) Description (Table P0040) 7 reserved 6 enable the selected (MREQ[7:4]#/PIRQ[3:0]# functionality 5 enable/disable configuration RAM Page Address (CPG[4:0]) generation =1 accesses to the configuration RAM space will generate the RAM page address on the LA[31:27]# pins (default) =0 the CPG[4:0] signals will not be activated 4 General Purpose Chip Selects: select GPCS[2:0]#/ECS[2:0] pins' function =0 GPCS[2:0]# functionality is selected =1 ESC[2:0] functionality is selected 3 System Error: enable generation of NMI based on SERR# signal pulsing =0 NMI is negated and SERR# is disabled from generating an NMI =1 NMI signal is asserted when NMIs are enabled via the NMIERTC Register and SERR# is asserted Note: other NMI sources are enabled/disabled via the NMISC register 2-0 PIRQx Mux/Mapping Control: select muxing/mapping of PIRQ[3:0]# with MREQ[7:4] and group of X-Bus signals (DLIGHT#, RTCWR#, RTCRD#). Different bit combinations select the number of EISA slots or group of X-Bus signals which can be supported with the certain number of PIRQx# signals by determining the functionality of pins AEN[4:1]/EAEN[4:1], MACK[3:0]#/EMACK[3:0]#, MREQ[7:4]/PIRQ[3:0]#, DLIGHT#/PIRQ0#, FDCCS#/PIRQ1#, RTCWR#/PIRQ2#, and RTCRD#/PIRQ3#. SeeAlso: #P0039 Bitfields for 82374EB BIOS Chip Select A "BIOSCSA" (register 42h): Bit(s) Description (Table P0041) 7-6 reserved 5 Enlarged BIOS: assert LBIOSCS# for memory read cycles to locations FFF80000h-FFFDFFFFh 4 High BIOS: assert LBIOSCS# for memory read cycles to locations 0F0000h-0FFFFFh, FF0000h-FFFFFFh, and FFFF0000h-FFFFFFFFh 3 Low BIOS 4: assert LBIOSCS# for memory read cycles to locations 0EC000h-0EFFFFh, FFEEC000h-FFEEFFFFh, and FFFEC000h-FFFEFFFFh 2 Low BIOS 3: assert LBIOSCS# for memory read cycles to locations 0E8000h-0EBFFFh, FFEE8000h-FFEEBFFFh, and FFFE8000h-FFFEBFFFh 1 Low BIOS 2: assert LBIOSCS# for memory read cycles to locations 0E4000h-0E7FFFh, FFEE4000h-FFEE7FFFh, and FFFE4000h-FFFE7FFFh 0 Low BIOS 1: assert LBIOSCS# for memory read cycles to locations 0E0000h-0E3FFFh, FFEE0000h-FFEE3FFFh, and FFFE0000h-FFFE3FFFh Note: if bit 3 of register 43h (BIOSCSB) is set, then LBIOSCS# will be asserted for write cycles as well as read cycles on any enabled range SeeAlso: #P0039,#P0042 Bitfields for 82374EB BIOS Chip Select B (register 43h): Bit(s) Description (Table P0042) 7-4 Reserved 3 BIOS Write Enable: assert LBIOSCS# for both memory read AND write cycles for addresses in the decoded and enabled BIOS range (see #P0041) 2 16 Meg BIOS: assert LBIOSCS# for memory read cycles to locations FF0000h-FFFFFFh 1 High VGA BIOS: assert LBIOSCS# for memory read cycles to locations 0C4000h-0C7FFFh 0 Low VGA BIOS: assert LBIOSCS# for memory read cycles to locations 0C0000h-0C3FFFh Note: if bit 3 of register 43h (BIOSCSB) is set, then LBIOSCS# will be asserted for write cycles as well as read cycles on any enabled range above SeeAlso: #P0039,#P0041 Bitfields for 82374EB EISA clock divisor (register 4Dh): Bit(s) Description (Table P0043) 7-6 Reserved 5 Co-processor Error: specify if the FERR# signal is connected to the ESC internal IRQ13 interrupt signal. =0 FERR# signal is ignored by the ESC (i.e. this signal is not connected to any logic in the ESC). =1 assert IRQ13 to the interrupt controller if FERR# signal is asserted 4 82374EB: Reserved 82374SB: ABFULL (with IRQ12): =0 internal IRQ12 is directed to the interrupt controller and transitions on ABFULL have no effect on this interrupt signal =1 the assertion of ABFULL is latched and directed to the internal IRQ12 signal in the following manner: If the interrupt controller is programmed for edge detect mode on IRQ12, a low-to-high transition is generated on the internal IRQ12 signal. Transitions on the IRQ12 input pin are not reflected on the internal IRQ12 signal. If the interrupt controller is programmed for level-sensitive mode, a high-to-low transition is generated on the internal IRQ12 signal. Transitions on the IRQ12 input pin are also reflected on the internal IRQ12 signal. The latching of the ABFULL signal is cleared by an I/O read of address 60h (no aliasing) or by a hard reset. 3 82374EB: Reserved 82374SB: Keyboard Full (KBFULL): select edge-detect KBFULL function on the IRQ1 input signal =0 IRQ1 is directed to the interrupt controller =1 (default) IRQ1 is latched and directed to the interrupt controller. The latched IRQ1 is cleared by an I/O read of address 60h (no aliasing) or by a hard reset. 2-0 Clock Divisor: select the integer used to divide the PCICLK down to generate the BCLK. 000 4 (33.33 MHz) 8.33 MHz (default after reset) 001 3 (25 MHz) 8.33 MHz 01x reserved 1xx reserved SeeAlso: #P0039 Bitfields for 82374EB peripheral Chip Select A (register 4Eh): Bit(s) Description (Table P0044) 7 Reserved 6 Keyboard Controller Mapping =0 the keyboard controller encoded chip select signal and the X-Bus transceiver enable (XBUSOE#) are generated for accesses to address locations 60h (82374EB/SB), 62h (82374EB only), 64h (82374EB/SB) and 66h (82374EB only). =1 the keyboard controller chip select signals are generated for accesses to the above address locations. However XBUSOE# is disabled. Note: bit 1 must be 1 for either value of this configuration bit to decode an access to locations 60h, 62h, 64h, or 66h. 5 Floppy Disk/IDE Controller Address range =0 primary (1Fxh and 3Fxh) =1 secondary (17xh and 37xh) 4 IDE DECODE: enable or disable IDE locations 1F0h-1F7h (primary) or 170h-177h (secondary) and 3F6h,3F7h (primary) or 376h,377h (sec). 82374EB: When this bit is set to 0, the IDE encoded chip select signals and the X-Bus transceiver signal (XBUSOE#) are not generated for these addresses. 82374SB: When this bit is set to 0, the IDE encoded chip select signals and the X-Bus transceiver signal (XBUSOE#) are not generated for addresses 1F0h-1F7h (primary) or 170h-177h (secondary) and 3F6h or 376h. Read/write accesses to addresses 377h and 3F7h are not disabled and still generate XBUSOE#. 3-2 Floppy Disk and IDE/Floppy Disk Decodes: Bits 2 and 3 are used to enable or disable the floppy locations as indicated. Bit 2 defaults to enabled (1) and bit 3 defaults to disabled (0) when a reset occurs 1 Keyboard Controller Decode: enable the keyboard controller address locations 60h (82374EB/SB), 62h (82374EB only), 64h (82374EB/SB), and 66h (82374EB only). =0 the keyboard controller encoded chip select signals and the X-Bus transceiver signal (XBUSOE#) are not generated for these locations Note: the value of this bit affects control function (keyboard controlling mapping) provided by bit 6 of this register. 0 Real Time Clock Decode: enable the RTC address locations 70h-77h. =0 the RTC encoded chip select signals RTCALE, RTCRD, RTCWR#, and XBUSOE# signals are not generated for these addresses. SeeAlso: #P0039,#P0045 Bitfields for 82374EB peripheral Chip Select B (register 4Fh): Bit(s) Description (Table P0045) 7 CRAM Decode: enable I/O write accesses to location 0C00h and I/O read/write accesses to locations 0800h-08FFh. The configuration RAM read and write (CRAMRD#, CRAMWR#) strobes are valid for accesses to 0800h-08FFh. 6 Port 92 Decode: enable access to Port 92 (default at PCIRST is enabled) 5-4 select which Parallel Port address range (LPT1, 2, or 3) is decoded. 00 LPT1 (3BCh-3BFh) 01 LPT2 (378h-37Fh) 10 LPT3 (278h-27Fh) 11 disabled 3-2 Serial Port B Address Decode: If either COM1 or COM2 address ranges are selected, these bits default to disabled upon PCIRST. 00 3F8h-3FFh (COM1) 01 2F8h-2FFh (COM2) 10 Reserved 11 Port B disabled 1-0 Serial Port A Address Decode: If either COM1 or COM2 address ranges are selected, these bits default to disabled upon PCIRST. 00 3F8h-3FFh (COM1) 01 2F8h-2FFh (COM2) 10 Reserved 11 Port A disabled SeeAlso: #P0039,#P0044 Bitfields for 82374SB PCI/APIC control (register 70h): Bit(s) Description (Table P0046) 7-2 Reserved 1 SMI Routing Control (SMIRC) =1 SMI is routed via the APIC =0 SMI is routed via the SMI# signal Note: when SMRCe1, INTR can not be routed through the APIC, since it is sharing the APIC interrupt input with SMI#. 0 INTR Routing Control (INTRC): When APIC is enabled (in mixed or pure APIC mode), this bit allows the ESC's external INTR signal to be masked (forces INTR to the inactive state but does not tri-states the signal). Thus, the CPU's INTR pin can be used (by providing a simple -gate) for the APIC Local Interrupt (LINTRx). However, INTR must not be masked via this bit when APIC is disabled and INTR is the only mechanism to signal the 8259 recognized interrupts to the CPU. =1 INTR is disabled (APIC must be enabled) =0 INTR is enabled SeeAlso: #P0039 Bitfields for 82374SB SMI control (register A0h): Bit(s) Description (Table P0047) 7 reserved (0) 6-4 reserved 3 Fast Off Timer Freeze (CTMRFRZ): disable the Fast Off Timer Disabling the timer prevents time-outs from occurring while executing SMM code. 2 STPCLK# Scaling Enable (CSTPCLKSC) =0 (default) scaling control of the STPCLK# signal is disabled. =1, the STPCLK# signal scaling control is enabled. When enabled (and bit 1=1, enabling the STPCLK# signal), the high and low times for the STPCLK# signal are controlled by the Clock Scaling STPCLK# High Timer and Clock Scaling STPCLK# Low Timer Registers, respectively. 1 STPCLK# Signal Enable (CSTPCLKE): permits software to place the CPU into a low power state. =0 (default) STPCLK# signal is disabled and is negated (high) =1 the STPCLK# signal is enabled and a read from the APMC Register causes STPCLK# to be asserted Software can set this bit to 0 by writing a 0 to it or by any write to the APMC Register. 0 SMI# Gate (CSMIGATE) =0 (default) the SMI# signal is masked and negated =1 SMI# signal is enabled and a system management interrupt condition causes the SMI# signal to be asserted Note: bit 0 only affects the SMI# signal and does not affect the detection/recording of SMI events (i.e., it does not affect the SMI status bits in the SMIREQ Register). Thus, SMI conditions can be pending when bit 0 is set to 1; if an SMI is already pending, the SMI# signal is asserted. SeeAlso: #P0039 Bitfields for 82374SB SMI enable (register A2h-A3h): Bit(s) Description (Table P0048) 15-8 Reserved 7 APMC Write SMI Enable =0 writes to the APMC Register do not generate an SMI =1 writes to the APMC Register generate an SMI 6 EXTSMI# SMI Enable =1 asserting the EXTSMI# input signal generates an SMI 5 Fast Off Timer SMI Enable =1 Fast-Off timer generates an SMI when it decrements to zero 4 IRQ12 SMI Enable (PS/2 Mouse Interrupt) =1 asserting the IRQ12 input signal generates an SMI 3 IRQ8 SMI Enable (RTC Alarm Interrupt) =1 asserting the IRQ8 input signal generates an SMI 2 IRQ4 SMI Enable (COM2/COM4 Interrupt or Mouse) =1 asserting the IRQ3 input signal generates an SMI 1 IRQ3 SMI Enable (COM1/COM3 Interrupt or Mouse) =1 asserting the IRQ3 input signal generates an SMI 0 IRQ1 SMI Enable (Keyboard Interrupt) =1 asserting the IRQ1 input signal generates an SMI SeeAlso: #P0039 Bitfields for 82374SB System Event Enable (register A4h-A7h): Bit(s) Description (Table P0049) 31 Fast Off SMI Enable (FSMIEN) =1 an SMI causes a system event that re-loads the Fast Off Timer and a break event that negates the STPCLK# signal =0 an SMI does not re-load the Fast Off Timer or negate the STPCLK# signal 30 reserved 29 Fast Off NMI Enable (FNMIEN) =1 an NMI (e.g., parity error) causes a system event that re-loads the Fast Off Timer and a break event that negates the STPCLK# signal =0 an SMI does not re-load the Fast Off Timer or negate the STPCLK# signal. 28-16 reserved 15-3 These bits are used to prevent the system from entering Fast Off and break any current powerdown state when the selected hardware interrupt (IRQ15-IRQ3) occurs =1 the corresponding interrupt causes a system event that re-loads the Fast Off Timer and a break event that negates the STPCLK# signal =0 the corresponding interrupt does not re-load the Fast Off Timer or negate the STPCLK# signal 2 reserved 1-0 These bits are used to prevent the system from entering Fast Off and break any current powerdown state when the selected hardware interrupt (IRQ1-IRQ0) occurs =1 the corresponding interrupt causes a system event that re-loads the Fast Off Timer and a break event that negates the STPCLK# signal =0 the corresponding interrupt does not re-load the Fast Off Timer or negate the STPCLK# signal SeeAlso: #P0039 Bitfields for 82374SB SMI Request (register AAh-ABh): Bit(s) Description (Table P0050) 15-8 Reserved 7 APM SMI Status (RAPMC): set to 1 to indicate that a write to the APM Control Register caused an SMI 6 EXTSMI# SMI Status (REXT): set to 1 when EXTSMI# caused an SMI 5 Fast Off Timer Expired Status (RFOT): set to 1 to indicate that the Fast Off Timer expired and caused an SMI. The Fast Off timer re-starts counting on the next clock after it expires. 4 SMI caused by IRQ12 3 SMI caused by IRQ8 2 SMI caused by IRQ4 1 SMI caused by IRQ3 0 SMI caused by IRQ1 SeeAlso: #P0039 ----------P00220023-------------------------- PORT 0022-0023 - CHIPSET FROM ETEC CHEETAH ET6000 (SINGLE CHIP) 0022 RW chip set data 0023 ?W index for accesses to data port (see #P0051) (Table P0051) Values for Etec Cheetah ET6000 chip set register index: 10h system configuration register (see #P0052) 11h cache configuration & non-cacheable block size register (see #P0053) 12h non-cacheable block address register bit 7-1 non-cacheable address, A25-A19 bit 0 reserved 13h DRAM bank & type configuration register (see #P0054) 14h DRAM configuration register (see #P0055) 15h shadow RAM configuration register (see #P0056) Bitfields for Etec Cheetah ET6000 system configuration register: Bit(s) Description (Table P0052) 7-6 00 turbo/non-turbo 01 local device supported 10 suspend mode 11 illegal 5 reserved 4 refresh selection 0 = AT type refresh 1 = concurrent refresh 3 slow refresh 95mSec enabled 2 fast reset delay 0 = do not use delay 1 = wait for 2mSec delay 1 wait for HALT after KBDRST 0 RAM at A0000-BFFFF 0 = AT bus cycle 1 = local bus cycle SeeAlso: #P0051 Bitfields for Etec Cheetah ET6000 cache configuration register: Bit(s) Description (Table P0053) 7-5 000 disabled 001 512K 010 1M 011 2M 100 4M 101 8M 110 16M 111 32M 4 DRAM banks 0 = 2-bank DRAM 1 = 4-bank DRAM 3-0 reserved SeeAlso: #P0051 Bitfields for Etec Cheetah ET6000 DRAM bank & type configuration register: Bit(s) Description (Table P0054) 7-6 bank 3 DRAM type 00 none 01 256K 10 1M 11 4M 5-4 bank 2 DRAM type 3-2 bank 1 DRAM type 1-0 bank 0 DRAM type SeeAlso: #P0051 Bitfields for Etec Cheetah ET6000 DRAM configuration register: Bit(s) Description (Table P0055) 7 on-board memory range 15M to 16M disabled 6 on-board memory range 512K-640K disabled 5 ROM chip select at C0000-DFFFF enabled 4 RAS to CAS time 0 = 1 SYSCLCK, not for R0WS 1 = 2 SYSCLCK 3 RAS precharge time 0 = 1.5 SYSCLCK 1 = 2.5 SYSCLCK 2-1 read cycle wait state 00 = 0 wait state 01 = 1 ws 10 = 2 ws 11 = 3 ws 0 write cycle wait state 0 = 0 ws 1 = 1 ws SeeAlso: #P0051 Bitfields for Etec Cheetah ET6000 shadow RAM configuration register: Bit(s) Description (Table P0056) 7 shadow at C0000-FFFFF 0 = non-cacheable 1 = cacheable and cache-write-proteced 6 access ROM/RAM at F0000-FFFFF 0 = read from ROM, write to RAM 1 = read from shadow, write is protected 5 access ROM/RAM at E0000-EFFFF 0 = access on-board ROM, AT bus cycle 1 = access shadow E0000-EFFFF enabled 4 RAM at E0000-EFFFF is read-only 3 access ROM/RAM at D0000-DFFFF 0 = access on-board ROM, AT bus cycle 1 = access shadow D0000-DFFFF enabled 2 RAM at D0000-DFFFF is read-only 1 access ROM/RAM at C0000-CFFFF 0 = access on-board ROM, AT bus cycle 1 = access shadow C0000-CFFFF enabled 0 RAM at C0000-CFFFF is read-only SeeAlso: #P0051 ----------P00220023-------------------------- PORT 0022-0023 - Hewlett-Packard Hornet chipset (HP 100LX/200LX) 0022 RW index for accesses to data port (see Table P189) 0023 RW chip set data (Table P0057) Values for HP Hornet chipset register index: 1Eh buzzer volume/clock oscillator speed bit 7-6: buzzer volume bit 5-4: system oscillator speed 00: 10.738636MHz 01: 15.836773MHz(HP 100/200LX has oscillator with this speed) 10: 21.477272MHz 11: 31.673550MHz 21h display timing??? 23h LCD contrast (see INT15h AH=62h) valid values: 00h-1fh (1fh is the darkest) 51h power adapter status bit 7-1: ??? bit 0: power adapter status(0=inactive/1=active) 52h nicad charge status bit 7-3: ??? bit 2: battery charging status(0=???/1=slow charge) bit 1-0: ??? 53h nicad charge status bit 7-1: ??? bit 0: battery charging status(0=???/1=fast charge) 80h memory wait for internal ROM valid values: 00h-07h 81h memory wait for internal RAM valid values: 00h-03h 82h memory wait for external RAM valid values: 00h-0fh 87h battery status??? ----------P00220023-------------------------- PORT 0022-0023 - Chips&Technologies 82C100/110 - CONFIGURATION REGISTERS Note: each access to PORT 0023h must immediately follow a write to PORT 0022h (this is to avoid accidental accesses) 0022 -W configuration register index (see #P0058) 0023 RW configuration register data (Table P0058) Values for Chips&Technologies 82C100/110 configuration register index: 40h clock mode/size (see #P0059) 41h system configuration (see #P0060) 42h configuration valid (see #P0061) 43h DIP switch emulation (see #P0062) 44h-47h substitute NMI vector, bytes 0-3 (these specify the vector to be substituted at the INT 02 vector's memory address whenever an NMI occurs, preventing application software from modifying the NMI handler) 48h refresh timer counter (see #P0063) 49h wait state select, refresh enable, keyboard type (see #P0064) 4Ah reserved 4Bh sleep/memory configuration (see #P0065) 4Ch EMS configuration (see #P0066) 4Dh-4Fh reserved Bitfields for Chips&Technologies 82C100 clock mode/size register: Bit(s) Description (Table P0059) !!! !!!chips\82c110.pdf p.35 SeeAlso: #P0058 Bitfields for Chips&Technologies 82C100 system configuration register: Bit(s) Description (Table P0060) !!! SeeAlso: #P0058 Bitfields for Chips&Technologies 82C100 configuration valid register: Bit(s) Description (Table P0061) !!! SeeAlso: #P0058 Bitfields for Chips&Technologies 82C110 DIP Switch Emulation register: Bit(s) Description (Table P0062) !!!chips\82c110.pdf p.36 SeeAlso: #P0058 Bitfields for Chips&Technologies 82C100 refresh timer count register: Bit(s) Description (Table P0063) !!! SeeAlso: #P0058 Bitfields for Chips&Technologies 82C100 wait state select register: Bit(s) Description (Table P0064) !!! SeeAlso: #P0058 Bitfields for Chips&Technologies 82C100 sleep/memory configuration: Bit(s) Description (Table P0065) !!! SeeAlso: #P0058 Bitfields for Chips&Technologies 82C100 EMS configuration register: Bit(s) Description (Table P0066) !!! SeeAlso: #P0058 ----------P00220023-------------------------- PORT 0022-0023 - Chips&Technologies 82C235 "SCAT" - CONFIGURATION REGISTERS Note: each access to PORT 0023h must immediately follow a write to PORT 0022h (this is to avoid accidental accesses) 0022 -W configuration register index (see #P0067) 0023 RW configuration register data (Table P0067) Values for Chips&Technologies 82C235 configuration register index: 01h DMA wait-state control 40h version (read-only) 41h clock control 42h-43h reserved (but listed as read-write in docs) 44h peripheral control 45h miscellaneous status 46h power management 47h reserved 48h ROM enable 49h RAM write-protect control 4Ah shadow RAM enable 1 4Bh shadow RAM enable 2 4Ch shadow RAM enable 3 4Dh DRAM configuration 4Eh extended boundary 4Fh EMS control !!!chips\82c235.pdf p.87, p.140 ----------P00220023-------------------------- PORT 0022-0023 - Chips&Technologies 82C311 - CONFIGURATION REGISTERS Note: each access to PORT 0023h must immediately follow a write to PORT 0022h (this is to avoid accidental accesses) 0022 -W configuration register index (see #P0068) 0023 RW configuration register data (Table P0068) Values for Chips&Technologies 82C311 configuration register index: 04h version (read-only) !!!chips\82c311.pdf p.65 05h AT-bus command delay 06h AT-bus wait-state control 08h identification 09h low RAM/ROM configuration 0Ch memory enable map (80000h-9FFFFh) 0Dh memory enable map (A0000h-BFFFFh) 0Eh memory enable map (C0000h-DFFFFh) 0Fh memory enable map (E0000h-FFFFFh) 10h block 0 type and start address 11h block 0 DRAM timing 12h block 1 type and start address 13h block 1 DRAM timing 14h block 2 type and start address 15h block 2 DRAM timing 16h block 3 type and start address 17h block 3 DRAM timing 18h memory block types 20h cache control 21h directory RAM control 1 22h tag RAM directory address (low) 23h reference location 24h SRAM configuration/direct access address 25h directory RAM control 2 26h READY timeout 28h error source/address 29h error address (bits 23-16) 2Ah memory enable map (00000h-7FFFFh) 2Bh miscellaneous control 2Ch middle RAM/ROM configuration 2Fh page mode posted-write control (82C311 rev. C only) 30h block 0 non-cacheable address (bits 23-16) 31h block 0 non-cacheable address (bits 15-12) and size 32h block 1 non-cacheable address (bits 23-16) 33h block 1 non-cacheable address (bits 15-12) and size 34h block 2 non-cacheable address (bits 23-16) 35h block 2 non-cacheable address (bits 15-12) and size 36h block 3 non-cacheable address (bits 23-16) 37h block 3 non-cacheable address (bits 15-12) and size 38h block 0/1 non-cacheable addresses (bits 26-24) 39h block 2/3 non-cacheable addresses (bits 26-24) 60h fast reset control !!!chips\82c311.pdf p.76, p.115 ----------P00220023-------------------------- PORT 0022-0023 - Chips&Technologies 82C315 - CONFIGURATION REGISTERS Note: each access to PORT 0023h must immediately follow a write to PORT 0022h (this is to avoid accidental accesses) SeeAlso: PORT 0022h"82C311",PORT 0022h"82C316" 0022 -W configuration register index (see #P0069) 0023 RW configuration register data (Table P0069) Values for Chips&Technologies 82C315 configuration register index: 07h processor and bus clock source selection (see #P0070) Bitfields for C&T 82C315 clock source selection register: Bit(s) Description (Table P0070) 7-5 reserved (0) 4 80387 is present 3 processor clock select =0 CLK2IN =1 AT bus state machine clock 2-0 bus clock source select 000 CLK2IN/5 001 CLK2IN/4 010 CLK2IN/3 011 CLK2IN/2 100 ATCLK SeeAlso: #P0069 ----------P00220023-------------------------- PORT 0022-0023 - Chips&Technologies 82C316 - CONFIGURATION REGISTERS Note: each access to PORT 0023h must immediately follow a write to PORT 0022h (this is to avoid accidental accesses) SeeAlso: PORT 0022h"82C311",PORT 0022h"82C315",PORT 0022h"82C811" 0022 -W configuration register index (see #P0071) 0023 RW configuration register data (Table P0071) Values for Chips&Technologies 82C316 configuration register index: 01h clock/wait-state control !!!chips\cs8233.pdf p.178 26h RTC/NMI/Coprocessor reset !!!chips\cs8233.pdf p.231 71h programmable I/O port 1 address, bits 15-8 72h programmable I/O port 1 address, bits 7-0 73h programmable I/O port 1 enable 74h programmable I/O port 2 address, bits 15-8 75h programmable I/O port 2 address, bits 7-0 76h programmable I/O port 2 enable 77h programmable I/O port 3 address, bits 15-8 78h programmable I/O port 3 address, bits 7-0 79h programmable I/O port 3 enable SeeAlso: #P0069 --------h-P00220023-------------------------- PORT 0022-0023 - Chips&Technologies 82C811/82C812 - CONFIGURATION REGISTERS Note: each access to PORT 0023h must immediately follow a write to PORT 0022h (this is to avoid accidental accesses) SeeAlso: PORT 0022h"82C311",PORT 0022h"82C315" 0022 -W configuration register index (see #P0072) 0023 RW configuration register data (Table P0072) Values for Chips&Technologies 82C811/812 configuration register index: 60h (82C811) processor clock select (see #P0073) 61h (82C811) command delay (see #P0074) 62h (82C811) wait states (see #P0075) ---82C812--- 64h version (see #P0076) 65h ROM configuration 66h memory enable 1 67h memory enable 2 68h memory enable 3 69h memory enable 4 6Ah bank 0/1 enable 6Bh memory configuration 6Ch bank 2/3 enable 6Dh EMS base address 6Eh EMS address extension 6Fh miscellaneous !!!chips\cs8281.pdf p.48 Bitfields for C&T 82C811 processor clock select: Bit(s) Description (Table P0073) 7-6 82C811 release number (00 = initial release) 5 fast CPU reset initiated by changing this bit from 0 to 1 4 processor clock 0 CLK2IN (default) 1 BCLK 3 reserved 2 enable NMI generate on timeout of local-bus READY# signal 1 reserved 0 local-bus READY# signal timed out (128 clock cycles0 SeeAlso: #P0072,#P0074,#P0075 Bitfields for C&T 82C811 command delay register: Bit(s) Description (Table P0074) 7 enable additional address bus hold time 6 reserved (1) 5-4 AT-bus 16-bit memory access delay, in BCLK cycles (default = 0) 3-2 AT-bus 8-bit memory access delay, in BCLK cycles (default = 1) 1-0 I/O command delay, in BCLK cycles (default = 1) SeeAlso: #P0072,#P0073,#P0075 Bitfields for C&T 82C811 wait states register: Bit(s) Description (Table P0075) 7 80387sx is present 6 coprocessor is ready 5-4 AT-bus 16-bit cycle wait states (default = 3) 3-2 AT-bus 8-bit cycle wait states (00=two ... 11=five [default]) 1-0 bus clock (BCLK) 00 CLK2IN/2 (default) 01 CLK2IN/3 10 ATCLK 11 reserved SeeAlso: #P0072,#P0073,#P0074 Bitfields for C&T 82C812 version register: Bit(s) Description (Table P0076) 7 NEATsx memory controller (0 = 82C812) 6-5 82C812 revision (00 = initial release) 4-0 reserved SeeAlso: #P0072 --------h-P00220023-------------------------- PORT 0022-0023 - Chips&Technologies 84031/84035 - CONFIGURATION REGISTERS Note: each access to PORT 0023h must immediately follow a write to PORT 0022h (this is to avoid accidental accesses) SeeAlso: PORT 0022h"82C311",PORT 0022h"82C315" 0022 -W configuration register index (see #P0077) 0023 RW configuration register data (Table P0077) Values for Chips&Technologies 84031/84035 configuration register index: 01h (84035) IPC DMA controller wait states and clock (see #P0078) !!!chips\82310.pdf p.71 !!!chips\api22.pdf p.33 05h (84031) ISA-bus command delays (see #P0079) 06h (84031) ISA-bus wait states (see #P0080) 07h (84031) ISA-bus clock select (see #P0081) 08h (84035) performance control (see #P0082) 09h (84035) miscellaneous control (see #P0083) 0Ah (84035) DMA clock select (see #P0084) 10h (84031) DRAM timing (see #P0085) !!!chips\api22.pdf p.49 11h (84031) DRAM setup 12h (84031) block 0/1 DRAM configuration 13h (84031) block 2/3 DRAM configuration 14h (84031) DRAM block 0 start address 15h (84031) DRAM block 1 start address 16h (84031) DRAM block 2 start address 17h (84031) DRAM block 3 start address 18h (84031) video shadow / local bus control 19h (84031) shadow RAM read enable 1Ah (84031) shadow RAM write enable 1Bh (84031) ROMCS enable 1Ch (84031) soft reset / GATEA20 Bitfields for C&T 84035 IPC DMA controller configuration: Bit(s) Description (Table P0078) 7-6 reserved 5-4 wait states for 16-bit DMA 00 one (default) 01 two 10 three 11 four 3-2 wait states for 8-bit DMA (settings same as bits 5-4) 1 disable one-cycle delay of MEMR# signal after IOR# 0 DMA clock (0 = BUSCLK/2 [default], 1 = BUSCLK) SeeAlso: #P0077,#P0082 Bitfields for C&T 84031 ISA-bus command delays: Bit(s) Description (Table P0079) !!! SeeAlso: #P0077,#P0080,#P0081 Bitfields for C&T 84031 ISA-bus wait states: Bit(s) Description (Table P0080) !!! SeeAlso: #P0077,#P0079,#P0081 Bitfields for C&T 84031 ISA-bus clock select: Bit(s) Description (Table P0081) !!! SeeAlso: #P0077,#P0079,#P0080 Bitfields for C&T 84035 performance control: Bit(s) Description (Table P0082) 7 flush 486 cache during every slow-mode hold (keeps CPU from running out of L1 cache during holds) 6-0 width of CPU hold pulse in BUSCLKs (0-127) SeeAlso: #P0077,#P0078,#P0083 Bitfields for C&T 84035 miscellaneous control: Bit(s) Description (Table P0083) 7 floating-point error mode =0 generate IRQ13 internally on FERR# =1 use external logic to generate IRQ13 6 keyboard interrupt mode =0 receive IRQ1 directly on IRQ1 pin =1 receive IRQ1 over control link 5 disable GATEA20 emulation =0 A20 controlled solely by PORT 0092h =1 A20 is OR of PORT 0092h and emulated 8042 A20 control 4 A20M#/TEST# function =0 pin is TEST# input =1 pin is A29M# output 3 reserved 2 enable 8254 Timer 1 refresh requests clearing this bit prevents problems that may be caused by a refresh request which occurs during a reset sequence 1 use VL-bus-compatible preemptive arbitration for LGNT# 0 deturbo mode (enable CPU holds as specified by performance-control register) (see #P0082) Note: the documentation says that bit 6 should remain clear SeeAlso: #P0077,#P0082 Bitfields for C&T 84035 DMA clock select: Bit(s) Description (Table P0084) 7 disable internal real-time clock 6-4 reserved (0) 3-0 DMA clock 0000 SCLK/10 0001 SCLK/8 0010 SCLK/6 1000 SCLK/5 (use with 40 MHz SCLK) 1001 SCLK/4 (use with 33 MHz SCLK) 1010 SCLK/3 (use with 25 MHz SCLK) 1011 SCLK/2.5 (for 20 MHz SCLK) 1100 SCLK/2 (for 16 MHz SCLK) 1101 SCLK/1.5 else reserved Note: bits 3-0 should normally be set the same as register 07h bits 3-0 SeeAlso: #P0077 Bitfields for C&T 84031 DRAM timing: Bit(s) Description (Table P0085) 7-6 reserved (0) 5 4 3 2 !!! 1 reserved (0) 0 read timing 0 = 3-2-2-2 1 = 4-3-3-3 SeeAlso: #P0077,#P0086 Bitfields for C&T 84031 DRAM setup: Bit(s) Description (Table P0086) 7 enable DRAM parity (PORT 0061h bits 7 and 2 must also both be clear to enable parity) 6-4 reserved (0) 3-0 enable interleave for banks 3-0 (enabling interleave doubles address range for bank; banks 0/2 and 1/3 may be interleaved with each other) SeeAlso: #P0077,#P0085 ----------P00220023-------------------------- PORT 0022-0023 - OPTi 82C206 chipset - CONFIGURATION REGISTERS Note: many other OPTi chipsets integrate the functionality of the 82C206, and thus support the 82C206's configuration register (e.g. the 82C558 from the Viper chipset) 0022 ?W index for accesses to data port (set to 01h) 0023 RW chip set data Bitfields for OPTi 82C206 configuration register 01h: Bit(s) Description (Table P0087) 7-6 82C206 wait states 00 1 SYSCLK 01 2 SYSCLKs 10 3 SYSCLKs 11 4 SYSCLKs (default) 5-4 number of wait states for 16-bit DMA cycles 00 1 wait state (default) 01 2 wait states 10 3 wait states 11 4 wait states 3-2 number of wait states for 8-bit DMA cycles 00 1 wait state (default) 01 2 wait states 10 3 wait states 11 4 wait states 1 enable early DMAMEMR# 0 DMA speed 0 SYSCLK/2 1 SYSCLK ----------P00220023-------------------------- PORT 0022-0023 - Intel 82091AA Advanced Integrated Peripheral Range: PORT 0022h (X-Bus), PORT 0024h (X-Bus), PORT 026Eh (ISA), or PORT 0398h (ISA) SeeAlso: PORT 0024h"82091AA",PORT 026Eh"82091AA",PORT 0398h"82091AA" 0022 ?W configuration register index (see #P0088) 0023 RW configuration register data (Table P0088) Values for Intel 82091AA configuration register index: 00h product ID (read-only) A0h Intel 82091AA 01h product revision (read-only) (see #P0089) 02h configuration 1 (see #P0090) 03h configuration 2 (see #P0091) 04h-0Fh reserved 10h floppy-disk controller configuration (see #P0092) 11h floppy-disk controller power management/status (see #P0093) 12h-1Fh reserved 20h parallel port configuration (see #P0094) 21h parallel port power management/status (see #P0095) 22h-2Fh reserved 30h serial port A configuration (see #P0096) 31h serial port A power management/status (see #P0097) 32h-3Fh reserved 40h serial port B configuration (see #P0096) 41h serial port B power management/status (see #P0097) 42h-4Fh reserved 50h IDE configuration (see #P0098) 51h-FFh reserved Bitfields for Intel 82091AA product revision register: Bit(s) Description (Table P0089) 7-4 stepping number 3-0 "dash"-number SeeAlso: #P0088 Bitfields for Intel 82091AA configuration register 1: Bit(s) Description (Table P0090) 7 unused (0) 6 supply voltage (read-only) (1 = 3.3V, 0 = 5.0V) 5-4 configuration mode 00 software motherboard 01 software add-in 10 extended hardware 11 basic hardware 3 configuration address (read-only) 0 primary address (PORT 0022h for X-Bus, PORT 026Eh for ISA) 1 secondary address (PORT 0024h for X-Bus, PORT 0398h for ISA) 2-1 reserved 0 power-down AIP's main clock circuitry SeeAlso: #P0088,#P0091 Bitfields for Intel 82091AA configuration register 2: Bit(s) Description (Table P0091) 7-3 IRQ7-IRQ3 mode select 0 = active high (ISA-compatible tri-state drive) 1 = active low (EISA-compatible open-collector drive) 2-0 reserved SeeAlso: #P0088,#P0090 Bitfields for Intel 82091AA floppy-disk controller configuration register: Bit(s) Description (Table P0092) 7 four floppy drive support enabled (with external decoder) 6-2 reserved 1 FDC address 0 = primary (03F0h) 1 = secondary (0370h) 0 enable FDC SeeAlso: #P0088,#P0093 Bitfields for Intel 82091AA floppy-disk controller power management register: Bit(s) Description (Table P0093) 7-4 reserved 3 enable FDC auto-powerdown on idle 2 reset FDC (this bit must be pulsed, remaining high for at least 1.2 us) 1 (read-only) FDC is idle 0 power-down FDC Note: to restore FDC from explicit powerdown via bit 0, clear bit 0, then reset the FDC using bit 2 (hardware reset) or using a software reset (FDC's DOR bit 2 or DSR bit 7) SeeAlso: #P0088,#P0092 Bitfields for Intel 82091AA parallel port configuration: Bit(s) Description (Table P0094) 7 FIFO threshold 0 = 8 slots in each direction 1 = one slot forward, 15 reverse 6-5 parallel-port hardware mode 00 ISA-compatible 01 PS/2-compatible 10 EPP 11 ECP (read only -- ECP mode must be set via ECP Extended Control Reg) 4 reserved 3 IRQ select 0 = IRQ5 1 = IRQ7 2-1 address select 00 PORT 0378h-037Bh 01 PORT 0278h-027Bh 10 PORT 03BCh-03BEh (not for EPP mode) 11 reserved 0 enable parallel port SeeAlso: #P0088,#P0095,#P0920,PORT 0678h"ECP" Bitfields for Intel 82091AA parallel port power managment register: Bit(s) Description (Table P0095) 7-6 reserved 5 FIFO overrun or underrun has occurred this bit is cleared by resetting the port via bit 2 4 reserved 3 enable auto-powerdown 2 reset parallel port (pulse this bit; must remain high for 1.13 us) 1 (read-only) parallel port is idle 0 power-down parallel port Note: an explicit power-down may be canceled by either clearing bit 0 or pulsing bit 2 to reset the port SeeAlso: #P0088,#P0094 Bitfields for Intel 82091AA serial port configuration: Bit(s) Description (Table P0096) 7 enable 2MHz MIDI clock for MIDI baud rate 6-5 reserved 4 IRQ select 0 = IRQ3 1 = IRQ4 3-1 address select 000 PORT 03F8h-03FFh 001 PORT 02F8h-02FFh 010 PORT 0220h-0227h 011 PORT 0228h-022Fh 100 PORT 0238h-023Fh 101 PORT 02E8h-02EFh 110 PORT 0338h-033Fh 111 PORT 03E8h-03EFh 0 enable serial port Note: although it is possible to configure both serial ports at the same address, this is not recommended because the 82091AA disables serial port B without placing it into powerdown mode SeeAlso: #P0088,#P0097 Bitfields for Intel 82091AA serial port power management register: Bit(s) Description (Table P0097) 7-5 reserved 4 enable test mode when enabled, and DLAB bit in LCR is set, the baud rate clock is output on the SOUTA pin 3 enable auto-powerdown on idle 2 reset serial port (should be pulsed, high for at least 1.13 us) 1 (read-only) serial port is idle 0 power-down serial port Notes: setting powerdown mode via bit 0 resets both receiver and transmitter, including the FIFOs, so software should check that port is idle before powering it down the serial port may be brought out of an explicit powerdown by either clearing bit 0 or pulsing bit 2 SeeAlso: #P0088,#P0096 Bitfields for Intel 82091AA IDE configuration: Bit(s) Description (Table P0098) 7-3 reserved 2 enable both primary and secondary addresses 1 address select (when bit 2 is clear) 0 PORT 01F0h-01F7h and 03F6h (primary) 1 PORT 0170h-0177h and 0376h (secondary) 0 enable IDE interface !!!intel\29048603.pdf p.45 SeeAlso: #P0088,#P0092 ----------P00220024-------------------------- PORT 0022-0024 - CHIPSET FROM PICO POWER, UMC or PCChips 0022 ?W index for accesses to data port 0024 RW chip set data ----------P00220024-------------------------- PORT 0022-0024 - OPTi 82C281/282/283 CHIPSETS - CONFIGURATION REGISTERS Note: every access to PORT 0024h must be preceded by a write to PORT 0022h, even if the same register is being accessed a second time SeeAlso: PORT 0022h"82C206" 0022 ?W index for accesses to data port (see #P0099) 0024 RW chip set data (Table P0099) Values for OPTi 82C281/82C282/82C283 configuration register index: 10h DRAM configuration register (see #P0100) 11h Shadow RAM control register (see #P0101) 12h Shadow RAM control register 2 (see #P0102) 13h Shadow RAM control register 3 (see #P0103) 14h miscellaneous control register (see #P0104) 15h cache control register (see #P0105) 16h cache control register 2 (see #P0106) Bitfields for OPTi 82C281/282/283 DRAM configuration register: Bit(s) Description (Table P0100) 7-6 82C281/2 revision number (read-only) 7 82C283 revision (0 = A, 1 = B) 6 82C283A: reserved 82C283B: DRAM is pipelined 5 local DRAM read wait states 82C281/2: 0=one, 1=two 82C283: 0=none, 1=one 4 local DRAM write wait states 82C281/2: 0=one, 1=two 82C283: 0=none, 1=one 3-0 local DRAM memory configuration (val) Bank0 Bank1 Bank2 Bank3 0001 256K 256K 256K 256K 0010 256K 256K 1M - 0011 256K 256K 1M 1M 0100 256K 256K 4M - 0101 1M - - - 0110 1M 1M - - 0111 1M 1M 1M - 1000 1M 1M 1M 1M 1001 1M 4M - - 1010 1M 1M 4M - 1011 4M 4M - - 1100 4M - - - (82C283B only) 1111 256K 256K - - SeeAlso: #P0099 Bitfields for OPTi 82C281 shadow RAM control register: Bit(s) Description (Table P0101) 7 BIOS ROM F000-FFFF shadowing 0 read-only from shadow RAM 1 read from ROM, write to shadow RAM 6 adapter ROM at E000-EFFF 0 disable shadow RAM 1 shadow RAM selectively enabled by configuration register 12h (see #P0102) 5 adapter ROM at D000-DFFF 0 disable shadow RAM 1 shadow RAM selectively enabled by configuration register 12h 4 adapter ROM at C000-CFFF 0 disable shadow RAM 1 shadow RAM selectively enabled by configuration register 13h (see #P0103) 3 shadow RAM Copy Enable control (C000-EFFF) 0 write to expansion bus 1 write to local DRAM 2 shadow RAM E000-EFFF writeability 0 read/write 1 read-only 1 shadow RAM D000-DFFF writeability 0 read/write 1 read-only 0 shadow RAM C000-CFFF writeability 0 read/write 1 read-only SeeAlso: #P0099,#P0102 Bitfields for OPTi 82C281 shadow RAM control register 2: Bit(s) Description (Table P0102) 7 enable EC00-EFFF 6 enable E800-EBFF 5 enable E400-E7FF 4 enable E000-E3FF 3 enable DC00-DFFF 2 enable D800-DBFF 1 enable D400-D7FF 0 enable D000-D3FF Note: bits 7-4 are only in effect when register 11h bit 6 is set; bits 3-0 are only in effect when register 11h bit 5 is set SeeAlso: #P0099,#P0101,#P0103 Bitfields for OPTi 82C281 shadow RAM control register 3: Bit(s) Description (Table P0103) 7 enable CC00-CFFF 6 enable C800-CBFF 5 enable C400-C7FF 4 enable C000-C3FF 3-0 unused shadow RAM remap address; supplies bits 23-20 of address at which to map A000-BFFFF and D000-EFFF is not used for shadowing (except if this field is set to 0, the remapping is disabled) SeeAlso: #P0099,#P0101,#P0102 Bitfields for OPTi 82C281 miscellaneous control register: Bit(s) Description (Table P0104) 7 allow F0000-F0FFF to be written even while F0000-FFFFF is write-protected ("Zenith mode") 6 keyboard reset control =1 HLT must be executed before 82C281 generates CPU reset from keyboard controller Reset command 5 master byte swap enable 4 82C281/2: fast NMI request 82C283A: reserved (0) 82C283B: ATCLK setting (=0 from register 14h bit 0; =1 CLK/8) 3 82C281/2/3A: reserved 82C283B: on-board DRAM parity error enable 2 enable slow refresh mode (every 95.5 us (281/282) or 63.6 us (283) instead of 15.9 us) 1 enable turbo switch function 0 clock select =0 ATCLK2 = CPUCLK2 / 6 =1 ATCLK2 = CPUCLK2 / 4 SeeAlso: #P0099 Bitfields for OPTi 82C281/82C282 cache control register: Bit(s) Description (Table P0105) 7 enable cache 6 reserved (0) 5 enable posted write (82C281 only) 4 ALL accesses are non-cacheable 3 reserved (0) 2-0 non-cacheable region size (see also #P0106) 000 64K 001 128K ... 101 4M 110 8M 111 disabled SeeAlso: #P0099,#P0106 Bitfields for OPTi 82C281/82C282 cache control register 2: Bit(s) Description (Table P0106) 7-0 starting address bits 23-16 of non-cacheable region Note: the specified starting address must be a multiple of the region size SeeAlso: #P0099,#P0105 ----------P00220024-------------------------- PORT 0022-0024 - OPTi 82C291/82C295 CHIPSETS - CONFIGURATION REGISTERS Note: every access to PORT 0024h must be preceded by a write to PORT 0022h, even if the same register is being accessed a second time SeeAlso: PORT 0022h"82C206" 0022 ?W index for accesses to data port (see #P0107) 0024 RW chip set data (Table P0107) Values for OPTi 82C291/82C295 configuration register index: 20h Revision/AT Bus configuration register (see #P0108) 21h System Control register (see #P0109) 22h DRAM configuration register (see #P0110) 23h ROM Chip Select Control register (see #P0111) 24h Shadow RAM control register E (see #P0112) 25h Shadow RAM control register D (see #P0113) 26h Shadow RAM control register C (see #P0114) 27h Shadow RAM Write Protect/Remap Area (see #P0115) 28h Cache Control register (see #P0116) 29h Cacheable Upper Bound register (see #P0117) 2Ah Non-Cacheable Segments register 1 (see #P0118) 2Bh Non-Cacheable Segments register 2 (see #P0119) 2Ch Non-Cacheable Segments register 3 (see #P0120) Bitfields for OPTi 82C291/82C295 AT Bus configuration register: Bit(s) Description (Table P0108) 7-6 82C291/295 revision (read-only) 5-4 back-to-back I/O recovery time 00-11 = 3-6 ATCLKs between I/O accesses 3 enable slow refresh mode 2 enable hidden refresh 1-0 AT clock selection 00 ATCLK = CLK2 / 10 01 ATCLK = CLK2 / 8 10 ATCLK = CLK2 / 6 11 ATCLK = CLK2 / 4 SeeAlso: #P0107 Bitfields for OPTi 82C291/82C295 System Control register: Bit(s) Description (Table P0109) 7 AT bus master byte swap enabled 6 ALE generation for each AT cycle 0 a new ALE will be generated during bus conversion cycles 1 multiple ALEs will be generated during bus conversion cycles 5 keyboard fast reset emulation control 0 enable, a "Halt" is required before a fast CPU reset is generated 1 disable, fast CPU reset is generated directly after the "FE" I/O command to port 64h is decoded 4 AT cycle additional wait state 0 disable, standard AT cycle 1 enable, inserts one extra wait state in standard AT bus cycle 3-2 reserved 1 local device ready control 0 RDYI# input to the 82C291 will be synchronized and set as RDY# to the CPU one T-state delayed 1 RDYI# input to the 82C291 will not be output to the CPU. RDY# from the local device must be directed to the 82C291 and the CPU 0 system memory parity checking 0 disable, no parity checking 1 enable, will check parity SeeAlso: #P0107 Bitfields for OPTi 82C291/82C295 DRAM Configuration register: Bit(s) Description (Table P0110) 7-6 number of DRAM read cycle wait states 5-4 number of DRAM write cycle wait states 3-0 Banks 0 thru 3 DRAM configuration (val) Bank0 Bank1 Bank2 Bank3 0000 256K 256KB - - 0001 256K 256K 256K 256K 0010 256K 256K 1M - 0011 256K 256K 1M 1M 0100 256K 256K 4M - 0101 1M - - - 0110 1M 1M - - 0111 1M 1M 1M - 1000 1M 1M 1M 1M 1001 1M 4M - - 1010 1M 1M 4M - 1011 4M - - - 1100 4M 4M - - 1101 reserved 1110 reserved 1111 reserved SeeAlso: #P0107 Bitfields for OPTi 82C291/82C295 ROM Chip Select Control register: Bit(s) Description (Table P0111) 7 enable ROM Chip Select for write cycles (to support flash ROMs) 6 enable ROMCS# for 0F0000-0FFFFF segments 5 enable ROMCS# for 0E8000-0EFFFF segments 4 enable ROMCS# for 0E0000-0E7FFF segments 3 enable ROMCS# for 0D8000-0DFFFF segments 2 enable ROMCS# for 0D0000-0D7FFF segments 1 enable ROMCS# for 0C8000-0CFFFF segments 0 enable ROMCS# for 0C0000-0C7FFF segments SeeAlso: #P0107 Bitfields for OPTi 82C291/82C295 Shadow RAM control register E: Bit(s) Description (Table P0112) 7 enable shadow RAM reads for EC000-EFFFF segments 6 enable shadow RAM reads for E8000-EBFFF segments 5 enable shadow RAM reads for E4000-E7FFF segments 4 enable shadow RAM reads for E0000-E3FFF segments 3 enable shadow RAM writes for EC000-EFFFF segments 2 enable shadow RAM writes for E8000-EBFFF segments 1 enable shadow RAM writes for E4000-E7FFF segments 0 enable shadow RAM writes for E0000-E3FFF segments Note: OPTi documentation incorrectly states the segment range for bits 5 and 1 as E4000-E7000. SeeAlso: #P0107 Bitfields for OPTi 82C291/82C295 Shadow RAM control register D: Bit(s) Description (Table P0113) 7 enable shadow RAM reads for DC000-DFFFF segments 6 enable shadow RAM reads for D8000-DBFFF segments 5 enable shadow RAM reads for D4000-D7FFF segments 4 enable shadow RAM reads for D0000-D3FFF segments 3 enable shadow RAM writes for DC000-DFFFF segments 2 enable shadow RAM writes for D8000-DBFFF segments 1 enable shadow RAM writes for D4000-D7FFF segments 0 enable shadow RAM writes for D0000-D3FFF segments Note: OPTi documentation incorrectly states the segment range for bits 5 and 1 as D4000-D7000. SeeAlso: #P0107 Bitfields for OPTi 82C291/82C295 Shadow RAM control register C: Bit(s) Description (Table P0114) 7 enable shadow RAM reads for CC000-CFFFF segments 6 enable shadow RAM reads for C8000-CBFFF segments 5 enable shadow RAM reads for C4000-C7FFF segments 4 enable shadow RAM reads for C0000-C3FFF segments 3 enable shadow RAM writes for CC000-CFFFF segments 2 enable shadow RAM writes for C8000-CBFFF segments 1 enable shadow RAM writes for C4000-C7FFF segments 0 enable shadow RAM writes for C0000-C3FFF segments Note: OPTi documentation incorrectly states the segment range for bits 5 and 1 as C4000-C7000. SeeAlso: #P0107 Bitfields for OPTi 82C291/82C295 Shadow RAM Write Protect/Remap Area: Bit(s) Description (Table P0115) 7 enable Write Protect for F0000-FFFFF segments 6 enable Write Protect for E0000-EFFFF segments 5 enable Write Protect for D0000-DFFFF segments 4 enable Write Protect for C0000-CFFFF segments 3-0 DRAM remap starting address, bits 23-20 0000 disabled, no mapping 0001 1M 0010 2M ... 1111 15M SeeAlso: #P0107 Bitfields for OPTi 82C291/82C295 Cache Control register: Bit(s) Description (Table P0116) 7 enable write-back cache controller operation 6 enable DRAM performance mode this bit should not be enabled unless external cache is disabled (intended to optimize DRAM performance) 5 enable all memory accesses no-cacheable mode 4 enable 640K-1M area no-cacheable mode 3-2 cache timing control bits 00 invalid 01 0 wait state cache write w/o CAWE# extended, use when 8K*8 SRAMs 10 1 wait state cache write hit 11 0 wait state cache write hit with CAWE# extended when 32K*8 SRAMs 1-0 cache size/cacheable DRAM 00 16K / 2M 01 32K / 4M 10 64K / 8M 11 128K / 16M SeeAlso: #P0107 Bitfields for OPTi 82C291/82C295 Cacheable Upper Bound register: Bit(s) Description (Table P0117) 7-4 reserved 3-0 cacheable upper bound address, bits 23-20 0000 feature disabled 0001 1M 0010 2M ... 1111 15M SeeAlso: #P0107 Bitfields for OPTi 82C291/82C295 Non-Cacheable Segments register 1: Bit(s) Description (Table P0118) 7 enable non-cacheable segment A 6-4 size of no-cacheable memory segment A 000 64K 001 128K 010 256K 011 512K 100 1M 101 2M 110 4M 111 8M 3 enable non-cacheable segment B 2-0 size of no-cacheable memory segment B (same values as bits 6-4) SeeAlso: #P0107,#P0119 Bitfields for OPTi 82C291/82C295 Non-Cacheable Segments register 2: Bit(s) Description (Table P0119) 7-0 address bits 23-16 for starting address of non-cacheable memory segment A SeeAlso: #P0107,#P0118,#P0120 Bitfields for OPTi 82C291/82C295 Non-Cacheable Segments register 3: Bit(s) Description (Table P0120) 7-0 address bits 23-16 for starting address of non-cacheable memory segment B SeeAlso: #P0107,#P0118,#P0119 ----------P00220024-------------------------- PORT 0022-0024 - OPTi 82C381/82C382 CHIPSETS - CONFIGURATION REGISTERS Note: every access to PORT 0024h must be preceded by a write to PORT 0022h, even if the same register is being accessed a second time SeeAlso: PORT 0022h"82C206" 0022 ?W index for accesses to data port (see #P0121) 0024 RW chip set data (Table P0121) Values for OPTi 82C381/82C382 configuration register index: 00h clock selects (see #P0122) 01h reset control (see #P0123) 10h remapping address (see #P0124) 11h shadow RAM (see #P0125) 12h memory enable (see #P0126) 13h bank configuration (see #P0127) 14h DRAM configuration (see #P0128) 15h video adapter shadow (see #P0129) 16h fast GateA20 (see #P0130) 17h cache configuration (see #P0131) 18h non-cacheable block 1 size (see #P0132) 19h non-cacheable block 1 address (see #P0133) 1Ah non-cacheable block 2 size (see #P0132) 1Bh non-cacheable block 2 address (see #P0133) 1Ch cacheable area (see #P0134) Note: registers 00h and 01h address the 82C381, the remaining registers address the 82C382 SeeAlso: #P0189 Bitfields for OPTi 82C381/82C382 clock selects: Bit(s) Description (Table P0122) 7-6 cache controller enable 00 cache controller disabled (default) 01 cache controller disabled; PPCS#, SPCS#, NPCS# signals are active if selected 10 external cache controller installed 11 on-chip cache controller installed 5 hot CPU reset (low->high transition generates reset) 4 enable ATCLK stretch 3 turbo clock =0 CLKIN is CPU clock =1 HIGH pin selected clock (HIGH=0: CLKIN, HIGH=1: ICLK) 2-1 ICLK clock select 00 CLKIN/4 (default) 01 CLKIN/3 10 CLKIN/2 11 reserved 0 master byte swap enable (default = 0) SeeAlso: #P0121,#P0123 Bitfields for OPTi 82C381/82C382 reset control: Bit(s) Description (Table P0123) 7-2 reserved 1 RESET3 control =1 generate RESET3 on RESET2 only after a HLT instruction =0 generate RESET3 immediately on RESET2 (default) 0 activate cache controller FLUSH# pin (default = 1) SeeAlso: #P0121,#P0122,#P0124 Bitfields for OPTi 82C381/82C382 remapping address: Bit(s) Description (Table P0124) 7-5 reserved 4 enable remapping 3-0 remap address range, bits 23-20 0000 no mapping 0001 1M 0010 2M ... 1111 15M SeeAlso: #P0121 Bitfields for OPTi 82C381/82C382 shadow RAM control: Bit(s) Description (Table P0125) 7 BIOS ROM at F0000-FFFFF Shadowing 0 read only from shadow RAM 1 read from ROM, write to shadow RAM 6 ROM at D0000-DFFFF 0 disable shadow RAM 1 shadow RAM selectively enabled by configuration register 12h 5 Adaptor ROM at E0000-EFFFF 0 disable shadow RAM 1 shadow RAM selectively enabled by configuration register 12h 4 write-protect shadow RAM at D0000h-DFFFFh (default = not protected) 3 write-protect shadow RAM at E0000h-EFFFFh 2 enable Timeout precharge counter 1-0 reserved SeeAlso: #P0121 Bitfields for OPTi 82C381/82C382 memory enable: Bit(s) Description (Table P0126) 7 enable EC000-EFFFF 6 enable E8000-EBFFF 5 enable E4000-E7FFF 4 enable E0000-E3FFF 3 enable DC000-DFFFF 2 enable D8000-DBFFF 1 enable D4000-D7FFF 0 enable D0000-D3FFF Note: 0 = disable Shadow RAM (default), 1 = enable Shadow RAM SeeAlso: #P0121 Bitfields for OPTi 82C381/82C382 memory bank configuration: Bit(s) Description (Table P0127) 7 Reserved 6-4 Bank0 and Bank1 configuration (val) Bank0 Bank1 000 256K - 001 256K 256K 010 256K 1M 011 1M 256K 100 1M - 101 1M 1M 110 - - 111 256K - 3 reserved 2-0 Bank2 and Bank3 configuration (val) Bank2 Bank3 000 256K - 001 256K 256K 010 - - 011 1M 256K 100 1M - 101 1M 1M 11X - - SeeAlso: #P0121,#P0128 Bitfields for OPTi 82C381/82C382 DRAM configuration: Bit(s) Description (Table P0128) 7,6 number of read cycle wait states (default = 01) 5 write cycle wait state 0 = 0 wait 1 = 1 wait (default) 4-0 reserved SeeAlso: #P0121 Bitfields for OPTi 82C381/82C382 video adapter shadow: Bit(s) Description (Table P0129) 7 reserved 6 copy enable for C0000-EFFFF 0 write to AT Channel (default) 1 write to local DRAM 5 Shadow RAM at C0000-CFFFF writability 0 read/write (default) 1 read only 4 ROM at C0000-CFFFF 0 disable shadow RAM 1 shadow RAM selectively enabled by Bits<0:3> (default) 3 enable Shadow RAM at CC000-CFFFF 2 enable Shadow RAM at C8000-CbFFF 1 enable Shadow RAM at C4000-C7FFF 0 enable Shadow RAM at C0000-C3FFF SeeAlso: #P0121 Bitfields for OPTi 82C381/82C382 fast GateA20 control: Bit(s) Description (Table P0130) 7-4 Reserved 3 Fast GateA20 Control 0 Signal controled by GATEA20 signal from Keyboard Controler 1 CPUA20 enabled onto GA20 2-0 reserved SeeAlso: #P0121 Bitfields for OPTi 82C381/82C382 cache configuration: Bit(s) Description (Table P0131) 7 force NCA* Output Pin low if this bit is clear, it has no effect on NCA* Output Pin 6 enable Cache 5 write-through cache (Note: this bit must be set) 4-3 line size 00 4 bytes 01 8 bytes 10 16 bytes 11 reserved 2-0 reserved SeeAlso: #P0121 Bitfields for OPTi 82C381/82C382 non-cacheable block size: Bit(s) Description (Table P0132) 7-5 block size 000 64K 001 128K 010 256K 011 512K 100 1M 101 4M (block 1 only) 101 reserved (block 2 only) 110 8M (block 1 only) 110 reserved (block 2 only) 111 disabled (default) 4-0 reserved (0) SeeAlso: #P0121,#P0131,#P0133 Bitfields for OPTi 82C381/82C382 non-cacheable block address: Bit(s) Description (Table P0133) 7-0 bits 23-16 of non-cacheable block's address Note: the selected address must be a multiple of the block size selected by register 18h/1Ah SeeAlso: #P0121,#P0132,#P0134 Bitfields for OPTi 82C381/82C382 cacheable area: Bit(s) Description (Table P0134) 7-4 cacheable address range 0000 16M 0001 1M 0010 2M 0011 3M ... 1111 15M 3 256K remapped area is cacheable 2-0 reserved SeeAlso: #P0121 ----------P00220024-------------------------- PORT 0022-0024 - OPTi 82C463MV CHIPSET - CONFIGURATION REGISTERS Desc: the 82C463MV contains a memory control unit (MCU), an AT Bus Control Unit (BCU), a Power Management Unit (PMU), data buffers and a 82C206 type IPC (without real time clock) Note: every access to PORT 0024h must be preceded by a write to PORT 0022h, even if the same register is being accessed a second time SeeAlso: PORT 0022h"82C206" 0022 ?W index for accesses to data port (see #P0135) 0024 RW chip set data (Table P0135) Values for OPTi 82C463MV configuration register index: 30h general control 1 (see #P0136) 31h general control 2 (see #P0137) 32h shadow RAM control 1 (see #P0138) 33h shadow RAM control 2 (see #P0139) 34h DRAM size (see #P0140) 35h DRAM timing and caching control (see #P0141) 36h shadow RAM control 3 (see #P0142) 37h D000h and E000h segment access control (see #P0143) 38h non-cacheable block 1 size, controls and address bit A24 (see #P0144) 39h non-cacheable block 1 address bits A23-A16 3Ah non-cacheable block 2 size and address bit A24 (see #P0145) 3Bh non-cacheable block 2 address bits A23-A16 3Ch-3Fh reserved 40h PMU control 1 (see #P0146) 41h PMU control 2: doze timer (see #P0147) 42h PMU control 3: other timers (see #P0148) 43h PMU control 4 (see #P0149) 44h LCD timer count (should not be loaded with a value <5) 45h disk timer count (should not be loaded with a value <5) 46h keyboard timer count (should not be loaded with a value <5) 47h GNR_ACCESS timer count (should not be loaded with a value <5) 48h GNR_ACCESS I/O base address (lines A8-A1, A0 is a "don't care") 49h GNR_ACCESS control and I/O base address line A9 (see #P0150) 4Ah CSG0# base address (lines A8-A1, A0 is a "don't care") 4Bh CSG0# control and base address line A9 (see #P0151) 4Ch CSG1# base address (lines A8-A1, A0 is a "don't care") 4Dh CSG1# control and base address line A9 (see #P0152) 4Eh idle timer control (see #P0153) 4Fh idle timer count (should not be loaded with a value <5) 50h suspend/resume control (see #P0154) 51h beeper/sequencer control (see #P0155) 52h PMU general-purpose storage 1 53h PMU general-purpose storage 2 54h PMU Periferal Power (PPWR) control 1 (see #P0156) 55h PMU Periferal Power (PPWR) control 2 (see #P0157) 56h PIO control 1 (see #P0158) 57h PIO control 2 (see #P0159) 58h PMU event control 1 (see #P0160) 59h PMU event control 2 (see #P0161) 5Ah PMU event control 3 (see #P0162) 5Bh PMU event control 4 (see #P0163) 5Ch SMI source (low) (see #P0164) 5Dh SMI source (high) (see #P0165) 5Eh clock stretching control (see #P0166) 5Fh resume interrupt control (see #P0167) 60h software sequencer address (write only) 61h debounce control (see #P0168) 62h doze-mode IRQ selects (see #P0169) 63h idle timer IRQ selects (see #P0170) 64h PMI#6 IRQ select (see #P0171) 65h doze-mode configuration (see #P0172) 66h suspend control (see #P0173) 67h CPU frequency (see #P0174) 68h timer clock source (see #P0175) 69h R_TIMER count (should not be loaded with a value <5) 6Ah resume IRQ selects (see #P0176) 6Bh resume sources (see #P0177) 6Ch-6Fh TMP0 - TMP3 Bitfields for 82C463MV general control 1 (register 30h): Bit(s) Description (Table P0136) 7-6 chipset revision number (read only) 5 MASTER#/RI pin function (RI = modem Ring Indicator) =1 RI (default) =0 MASTER# 4 enable turbo VGA 3 enable global relocation/translation for SMI addresses (see also register 31h bit 4 at #P0137) 2 enable extra wait state in AT cycle 1 fast reset control =1 does not require Halt instruction =0 requires Halt instruction before generation of CPURST (SRESET if Intel SL Enhanced or Cyrix Cx486S/S2 CPUs 0 reserved (0) SeeAlso: #P0135 Bitfields for 82C463MV general control 2 (register 31h): Bit(s) Description (Table P0137) 7 enable master byte swap 6 reserved, read-only (1) 5 disable parity check 4 Dynamic SMI relocation if no SMI sequence is running =1 allow relocation of addresses from the CPU in the 3000h/4000h segment to the B000h/A000h SMI memory space =0 disable relocation if SMI sequence is running (qualified by SMIACT#) =1 allow data accesses to the 3000h and 4000h segments =0 relocate all accesses in the 3000h/4000h segment to the B000h/A000h SMI segment (normal operation) if SMI sequence is running (qualified by SMIADS#) =1 not allowed =0 for a SMIADS# cycle, relocate all accesses in the 6000h/7000h segment to the A000h/B000h SMI segment for a normal ADS# operation, there is no relocation 3 EC000h-EFFFFh access control if register 36h bit 6=0 =1 R/W from ROMCS# =0 R/W from AT-Bus if register 36h bit 6=1 =1 Read from ROMCS# if not shadowed (see register 33h bits 7-4), write to DRAM =0 Read from AT-Bus if not shadowed (see register 33h bits 7-4), write to DRAM 2 E8000h-EBFFFh access control (see bit 3) 1 E4000h-E7FFFh access control (see bit 3) 0 E0000h-E3FFFh access control (see bit 3) SeeAlso: #P0135,#P0139,#P0142 Bitfields for 82C463MV shadow RAM control 1 (register 32h): Bit(s) Description (Table P0138) 7 segment F000h access control =1 read from ROMCS#, write to ROMCS# (if register 36h bit 7=1) or DRAM (if register 36h bit 7=0) =0 read from DRAM and write protect (enable shadowing) 6-5 reserved (1) 4 write protect segment D000h 3 write protect segment E000h 2 reserved, read-only (1) 1 reserved (0) 0 ALE control =1 single ALE during bus conversion =0 multiple ALE SeeAlso: #P0135,#P0142,#P0139 Bitfields for 82C463MV shadow RAM control 2 (register 33h): Bit(s) Description (Table P0139) 7 enable shadowing for EC000h-EFFFFh 6 enable shadowing for E8000h-EBFFFh 5 enable shadowing for E4000h-E7FFFh 4 enable shadowing for E0000h-E3FFFh 3 enable shadowing for DC000h-DFFFFh 2 enable shadowing for D8000h-DBFFFh 1 enable shadowing for D4000h-D7FFFh 0 enable shadowing for D0000h-D3FFFh SeeAlso: #P0135,#P0138 Bitfields for 82C463MV DRAM size (register 34h): Bit(s) Description (Table P0140) 7-4 DRAM Bank 0 and 1 Size 0000 256K, unused 0001 256K, 256K 0010 256K, 1M 0011 256K, 4M 0100 512K, unused 0101 512K, 512K 0110 512K, 1M 0111 512K, 4M 1000 1M, unused 1001 1M, 1M 1010 1M, 4M 1011 4M, 1M 1100 4M, unused 1101 4M, 4M 1110 1M, 2M 1111 both unused 3-0 DRAM Bank 2 and 3 Size 0000 1M, unused 0001 1M, 1M 0010 1M, 4M 0011 4M, 4M 0100 4M, unused 0101 both unused 0110 1M, 2M 0111 512K, 512K 10xx both unused 110x both unused 1110 2M, unused 1111 2M, 2M (default) SeeAlso: #P0135 Bitfields for 82C463MV DRAM timing and caching control (register 35h): Bit(s) Description (Table P0141) 7-6 DRAM read wait states 00 = 0 wait states, burst mode 2-1-1-1 01 = 1 wait state, burst mode 3-1-1-1 10 = 1 wait state, burst mode 3-2-2-2 11 = 2 wait states, burst mode 4-3-3-3 (default) 5-4 DRAM write wait states 00 = 0 wait states 01 = 1 wait state 10 = 2 wait states 11 = reserved (default) 3 MP2/STRAP2 status (read-only) =1 1X Clock =0 2X Clock 2 disable caching of F000h segment (this bit is effective only when register 32h bit 7 =0) 1 global DRAM cache control (1=disable, default) 0 disable caching of C0000h-C7FFFh (default) SeeAlso: #P0135,#P0138 Bitfields for 82C463MV shadow RAM control 3 (register 36h): Bit Description (Table P0142) 7 segment F000h write control =1 write to ROMCS# =0 write to DRAM don't care if register 32h bit 7=0 6 C0000h-EFFFFh control =1 read from AT-Bus or ROMCS# (if ROMCS# is enabled to that block), write to DRAM =0 R/W from AT bus or ROMCS# (if ROMCS# is enabled to that block) 5 write protect segment C000h 4 reserved (1) 3 enable shadowing for CC000h-CFFFFh 2 enable shadowing for C8000h-CBFFFh 1 enable shadowing for C4000h-C7FFFh 0 enable shadowing for C0000h-C3FFFh SeeAlso: #P0135,#P0138 Bitfields for 82C463MV D000h and E000h segments access control (register 37h): Bit Description (Table P0143) 7 DC000h-DFFFFh access control if register 36h bit 6=1 =1 read from ROMCS# if not shadowed, write to DRAM =0 read from AT-Bus if not shadowed, write to DRAM if register 36h bit 6=0 =1 R/W from ROMCS# =0 R/W from AT-Bus 6 D8000h-DBFFFh access control (see bit 7) 5 D4000h-D7FFFh access control (see bit 7) 4 D0000h-D3FFFh access control (see bit 7) 3 disable caching for EC000h-EFFFFh (default) 2 disable caching for E8000h-EBFFFh (default) 1 disable caching for E4000h-E7FFFh (default) 0 disable caching for E0000h-E3FFFh (default) SeeAlso: #P0135,#P0142 Bitfields for non-cacheable block 1 size, control and A24 (register 38h): Bit(s) Description (Table P0144) 7-5 size of non-cacheable memory block 1 000 64K 001 128K 010 256K 011 1M 1xx disabled (default) 4 CC000h-CFFFFh access control if register 36h bit 6=1 =1 read from ROMCS# if not shadowed, write to DRAM =0 read from AT-Bus if not shadowed, write to DRAM if register 36h bit 6=0 =1 R/W from ROMCS# =0 R/W from AT-Bus 3 C8000h-CBFFFh access control (see bit 4) 2 C4000h-C7FFFh access control (see bit 4) 1 C0000h-C3FFFh access control (see bit 4) 0 address bit A24 of non-cacheable memory block 1 SeeAlso: #P0135,#P0142 Bitfields for non-cacheable block 2 size and A24 (register 3Ah): Bit(s) Description (Table P0145) 7-5 size of non-cacheable memory block 2 000 64K 001 128K 010 256K 011 1M 1xx disabled (default) 4 unused 3 enable internal HLDA latch during stop clock (must be disabled before DMA transfers are performed) 2 reserved (1) 1 unused 0 address bit A24 of non-cacheable memory block 2 SeeAlso: #P0135 Bitfields for 82C463MV PMU control 1 (register 40h): Bit Description (Table P0146) 7 Reset/SMI indication (read-only) =1 the last read or fetch from address XXXFFFF0h was a SMIADS# cycle =0 the last read or fetch from address XXXFFFF0h was a regular ADS# cycle 6 divide global timer by 4 5 LLOWBAT polarity selector =1 low active =0 high active 4 LOWBAT polarity selector (see bit 5) 3 SQWIN input clock frequency =1 128KHz =0 32KHz 2 external EPMI2 pin polarity =1 active low =0 active high 1 external EPMI1 pin polarity (see bit 2) 0 send reset pulse during resume Note: for 1X clock with Intel SL Enhanced CPU, bit 6 must be =1 SeeAlso: #P0135,#P0147,#P0148 Bitfields for 82C463MV PMU control 2 (doze timer, register 41h): Bit(s) Description (Table P0147) 7-5 hardware doze time-out selector 101 512 ms 110 2 sec 111 8 sec 4-2 hardware doze-mode CPU clock selector 000 CPUCLK/1 001 CPUCLK/2 010 CPUCLK/4 011 CPUCLK/8 (should be used during CPU stop clock only) 100 CPUCLK/16 (should be used during CPU stop clock only) 101 CPUCLK/3 110 reserved 111 reserved 1 enable LCD_ACCESS, KBD_ACCESS, DSK_ACCESS access to auto trigger the hardware doze timer 0 disable hardware doze-mode (enable APM doze-mode support) SeeAlso: #P0135,#P0146,#P0148 Bitfields for 82C463MV PMU control 3 (timers other than doze, register 42h): Bit(s) Description (Table P0148) 7-6 clock source for general-purpose timer 00 SQW0 01 SQW1 10 SQW2 11 SQW3 5-4 clock source for keyboard timer (see bits 7-6) 3-2 clock source for disk timer (see bits 7-6) 1-0 clock source for LCD timer (see bits 7-6) SeeAlso: #P0135,#P0147,#P0149 Bitfields for 82C463MV PMU control 4 (register 43h): Bit(s) Description (Table P0149) 7 disable monitoring of PORT 3B0h-3DFh 6 disable monitoring of memory range A0000h-BFFFFh 5-4 LOWBAT pin sample rate if register 40h bit 6 =1 00 32 seconds 01 64 seconds 10 128 seconds 11 reserved if register 40h bit 6 =0 00 8 seconds 01 16 seconds 10 32 seconds 11 reserved 3 reserved (0) 2-0 AT clock select 000 OSCCLK2/8 001 OSCCLK2/6 010 OSCCLK2/4 011 OSCCLK2/3 100 OSC14/2 (7.2 MHz) 111 stop SeeAlso: #P0135,#P0146,#P0149,#P0150 Bitfields for 82C463MV GNR_ACCESS control, I/O base address line A9 (reg. 49h): Bit(s) Description (Table P0150) 7 GNR_ACCESS I/O base address bit A9 6 enable compare in WRITE cycle 5 enable compare in READ cycle 4-0 I/O address A5-A1 mask bits. For each bit =1, the corresponding bit in register 48h is not compared (this is used to determine I/O address block size) SeeAlso: #P0135,#P0149 Bitfields for 82C463MV CSG0# control and base address line A9 (register 4Bh): Bit(s) Description (Table P0151) 7 Programmable Chip Select 0 (CSG0#) - I/O base address line A9 6 enable CSG0# for I/O write cycles 5 enable CSG0# for I/O read cycles 4 =1 CSG0# active before ALE =0 CSG0# active just like I/O command pulse 3-0 I/O address A4-A1 mask bits. For each bit =1, the corresponding bit in register 4Ah (bits 4-1) is not compared (this is used to determine I/O address block size) SeeAlso: #P0135,#P0152 Bitfields for 82C463MV CSG1# control and base address line A9 (register 4Dh): Bit(s) Description (Table P0152) 7 Programmable Chip Select 1 (CSG1#) - I/O base address line A9 6 enable CSG1# for I/O write cycles 5 enable CSG1# for I/O read cycles 4 =1 CSG1# active before ALE =0 CSG1# active just like I/O command pulse 3-0 I/O address A4-A1 mask bits. For each bit =1, the corresponding bit in register 4Ch (bits 4-1) is not compared (this is used to determine I/O address block size) SeeAlso: #P0135,#P0151 Bitfields for OPTi 82C463MV idle timer control (register 4Eh): Bit Description (Table P0153) 7 CSG1 access 6 CSG0 access 5 LPT access (it refers to PORT 378h-37Fh, PORT 278h-27Fh and PORT 3BCh-3BFh) 4 COM access (it refers to PORT 3F8h-3FFh and PORT 2F8h-2FFh) 3 GNR_ACCESS 2 KBD_ACCESS 1 DSK_ACCESS 0 LCD_ACCESS Note: If a bit is =1, the corresponding access will reload IDLE_TIMER otherwise not. SeeAlso: #P0135 Bitfields for 82C463MV suspend/resume control (register 50h): Bit Description (Table P0154) 7 software generation of SMI (enabled by bit 7 of register 59h) writing 1 asserts SMI to CPU to start SMM operation writing 0 clears the SMI (the SMI routine must clear this bit) 6 reserved (0) 5 IRQ8 active level =1 high active =0 low active 4 disable the internal 14.3MHz clock (to conserve power) 3 start doze-mode / read DOZE_TIMER status write: start APM doze-mode =1 start doze-mode (if register 40h bit 0 =1) =0 no effect read: hardware DOZE_TIMER time-out status bit =1 hardware DOZE_TIMER has timed out =0 hardware DOZE_TIMER still counting 2 Ready To Resume (RTR), read-only 1 PMU mode (read-only) =1 suspend-mode still active =0 all other modes 0 start suspend-mode (write only) =1 start suspend-mode =0 no effect SeeAlso: #P0135,#P0146,#P0161 Bitfields for 82C463MV beeper/sequencer control (register 51h): Bit(s) Description (Table P0155) 7-2 sequencer base address translated-to A17-A12 (A19-A18 are always 1 during this operation) 1-0 beeper control (independent from PORT 61h) if register 40h bit 6 =1 00 no action 01 1KHz 10 off 11 2KHz if register 40h bit 6 =0 00 no action 01 4KHz 10 off 11 8KHz SeeAlso: #P0135,#P0146 Bitfields for 82C463MV PMU Periferal Power (PPWR) control 1 (register 54h): Bit(s) Description (Table P0156) 7-4 write mask of PPWR low nibble =1 enable write on corresponding bit =0 write disable 3-0 read/write data bits for PPWR (low nibble) SeeAlso: #P0135,#P0157 Bitfields for 82C463MV PMU Periferal Power (PPWR) control 2 (register 55h): Bit(s) Description (Table P0157) 7-4 write mask of PPWR high nibble =1 enable write on corresponding bit =0 write disable 3-0 read/write data bits for PPWR (high nibble) (default =1) SeeAlso: #P0135,#P0156 Bitfields for OPTi 82C463MV PIO control 1 (register 56h): Bit(s) Description (Table P0158) 7-4 write mask of PIO bits 3-0 =1 enable write on corresponding bit =0 write disable 3-0 read/write data bits for PIO SeeAlso: #P0135,#P0159,#P0173 Bitfields for OPTi 82C463MV PIO control 2 (register 57h): Bit Description (Table P0159) 7 enable refresh (BIOS must set this bit to 1 after power up) 6 enable interrupts to generate PMI #6 (see also #P0167,#P0171) 5 disable monitoring floppy drive accesses 4 disable monitoring hard drive accesses 3 PIO3/STPGNT# pin direction =1 output =0 input 2 PIO2/CPUSPD pin direction (see bit 3) 1 PIO1/NOWS# pin direction (see bit 3) 0 PIO0 pin direction (see bit 3) SeeAlso: #P0135,#P0158 Bitfields for OPTi 82C463MV PMU event control 1 (register 58h): Bit(s) Description (Table P0160) 7-6 LOWBAT PMI #3 configuration 00 disable 01 sequencer 10 reserved 11 SMI 5-4 EPMI2 PMI #2 configuration (see bits 7-6) 3-2 EPMI1 PMI #1 configuration (see bits 7-6) 1-0 LLOWBAT PMI #0 configuration (see bits 7-6) SeeAlso: #P0135 Bitfields for OPTi 82C463MV PMU event control 2 (register 59h): Bit(s) Description (Table P0161) 7 global software SMI enable (see also bit 7 of register 50h at #P0154) 6 reload timers during a resume sequence 5-4 resume or INTR PMI #6 and Suspend PMI #7 configuration 00 disable 01 sequencer 10 reserved 11 SMI 3-2 R_TIMER PMI #5 configuration (see bits 5-4) 1-0 IDLE_TIMER PMI #4 configuration (see bits 5-4) SeeAlso: #P0135 Bitfields for OPTi 82C463MV PMU event control 3 (register 5Ah): Bit(s) Description (Table P0162) 7-6 GNR_TIMER time out PMI #11 and access PMI #15 configuration 00 disable 01 sequencer 10 reserved 11 SMI 5-4 KBD_TIMER time out PMI #10 and access PMI #14 cfg (see bits 7-6) 3-2 DSK_TIMER time out PMI #9 and access PMI #13 cfg (see bits 7-6) 1-0 LCD_TIMER time out PMI #8 and access PMI #12 cfg (see bits 7-6) SeeAlso: #P0135,#P0163 Bitfields for OPTi 82C463MV PMU event control 4 (register 5Bh): Bit Description (Table P0163) 7 IRQ15 SMI select =1 enable SMI select (SMI internally connected to IRQ15) and disable IRQ15 hardware pin function =0 disable SMI select (enable IRQ15 pin function as normal) 6 disable all SMI 5 enable sequencer 4 SMI Type =0 Intel style SMI (SMM identified by SMIACT#) =1 AMD DXLV or Cyrix style SMI (SMM identified by SMIADS#) Note: for Intel-style SMI, the 3000h/4000h segments will relocate to B000h/A000h when in SMM; for AMD/Cyrix, the 7000h/6000h segments will relocate to B000h/A000h when in SMM 3 enable PMI source #15 2 enable PMI source #14 1 enable PMI source #13 0 enable PMI source #12 SeeAlso: #P0135,#P0162,#P0164 Bitfields for OPTi 82C463MV SMI source (low) (register 5Ch): Bit Description (Table P0164) 7 PMI #7 - SUSPEND 6 PMI #6 - RESUME or INTR 5 PMI #5 - R_TIMER time out 4 PMI #4 - IDLE_TIMER time out 3 PMI #3 - LOWBAT pin 2 PMI #2 - EPMI2 pin (external PMI source) 1 PMI #1 - EPMI1 pin (external PMI source) 0 PMI #0 - LLOWBAT pin SeeAlso: #P0135,#P0165 Bitfields for OPTi 82C463MV SMI source (high) (register 5Dh): Bit Description (Table P0165) 7 PMI #15 - GNR_ACCESS 6 PMI #14 - KBD_ACCESS 5 PMI #13 - DSK_ACCESS 4 PMI #12 - LCD_ACCESS 3 PMI #11 - GNR_TIMER 2 PMI #10 - KBD_TIMER 1 PMI #9 - DSK_TIMER 0 PMI #8 - LCD_TIMER SeeAlso: #P0135,#P0164 Bitfields for OPTi 82C463MV clock stretching control (register 5Eh): Bit Description (Table P0166) 7 enable CPU clock stretch memory code cycle 6 enable CPU clock stretch write cycle 5 enable CPU clock stretch read cycle 4 enable CPU clock stretch I/O cycle 3 enable CPU clock stretch memory data cycle 2 enable stop ATCLK when not in AT bus cycle 1 ATCLK stretch =1 synchronous =0 asynchronous 0 reserved (0) SeeAlso: #P0135 Bitfields for OPTi 82C463MV resume interrupt control (register 5Fh): Bit(s) Description (Table P0167) 7 LCD_ACCESS includes AT bus video access 6 LCD_ACCESS includes Local bus video access 5 enable all resume sources of register 6Ah (see also #P0176,#P0159) 4 RI counter count out will generate resume 3-0 number of RI counts SeeAlso: #P0135 Bitfields for OPTi 82C463MV debounce control (register 61h): Bit(s) Description (Table P0168) 7-6 LOWBAT and LLOWBAT pin debounce rate select if register 40h bit 6 =1 00 no debounce 01 250 microseconds 10 8ms 11 500ms if register 40h bit 6 =0 00 no debounce 01 62.5 microseconds 10 2 ms 11 125 ms 5-4 SUSP/RSM pin debounce rate select if register 40h bit 6 =1 00 reserved 01 latch high to low edge 10 4 ms (low to high) 11 8 ms (low to high) if register 40h bit 6 =0 00 reserved 01 latch high to low edge 10 1 ms (low to high) 11 2 ms (low to high) 3 reserved (0) 2 enable STPCLK protocol for switching CPU clock frequencies 1-0 STPCLK# delay (for use when STPCLK protocol is enabled) 00 no delay 01 120 microseconds 10 240 microseconds 11 1ms, if register 40h bit 6 set; 240 microseconds if clear SeeAlso: #P0135,#P0146 Bitfields for OPTi 82C463MV doze-mode IRQ selects (register 62h): Bit Description (Table P0169) 7 enable IRQ13 6 enable IRQ8 5 enable IRQ7 4 enable IRQ12 3 enable IRQ5 2 enable IRQ4 1 enable IRQ3 0 enable IRQ0 Notes: in hardware doze-mode the selected interrupts will be used to re-load the hardware DOZE_TIMER and/or trigger the system out of doze-mode in APM doze-mode the selected interrupts will be used to trigger the system out of doze-mode only SeeAlso: #P0135,#P0172,#P0170 Bitfields for OPTi 82C463MV idle timer IRQ selects (register 63h): Bit Description (Table P0170) 7 enable EPMI1 (level trigger) 6 enable IRQ13 5 enable IRQ8 4 enable IRQ7 3 enable IRQ5 2 enable IRQ4 1 enable IRQ3 0 enable IRQ0 SeeAlso: #P0135,#P0169,#P0171 Bitfields for OPTi 82C463MV PMI#6 IRQ selects (register 64h): Bit Description (Table P0171) 7 enable IRQ14 6 enable IRQ8 5 enable IRQ7 4 enable IRQ6 3 enable IRQ5 2 enable IRQ4 1 enable IRQ3 0 enable IRQ1 Note: the value written into this register selects which IRQs generate PMI#6 in normal mode, the value read from this register indicates active IRQs at the time of the read SeeAlso: #P0135,#P0159,#P0170 Bitfields for OPTi 82C463MV doze-mode configuration (register 65h): Bit Description (Table P0172) 7 enable monitoring all interrupt signals during hw or sw doze-mode 6 doze-mode STPCLK protocol selector (see also #P0168) =1 STPCLK will latch for stopping the CPU clock (APM) The delay is determined by register 61h bits 1-0 =0 STPCLK will pulse for changing the frequency of the CPU clock (hw doze-mode). The pulse width is determined by register 61h bits 1-0 5 enable EPMI1 to reload hardware DOZE_TIMER and exit from hardware or software doze-mode 4 enable recognition of SMI during APM stop clock 3 allow IRQ1 to exit from hw or sw doze-mode (write-only) (see also #P0169) 2-0 reserved (0) SeeAlso: #P0135,#P0173 Bitfields for OPTi 82C463MV suspend control (register 66h): Bit Description (Table P0173) 7 refresh type during suspend =1 self refresh =0 normal refresh (refresh rate selected by register 67h bit 6) 6 KBCLK during suspend =1 16 KHz =0 7.16 MHz (14.318 MHz /2) 5 software (APM) CPU stop-clock control =1 the CPU clock can be stopped by entering APM doze-mode (that is setting register 50h bit 3 to 1) =0 APM doze-mode will use the hw doze-mode clock selected by bits 4-2 of register 41h 4 avoid asserting HOLD before stopping the clock 3 PIO3/STPGNT# pin selector =1 STPGNT# function (set register 57h bit 3 to input mode) This is for use with CPUs that use the hw stop grant signal to acknowledge stop request =0 PIO3 function (set register 57h bit 3 to determine input or output mode) 2 PIO2/CPUSPD pin selector =1 CPUSPD function, CPU speed indicator output (set register 57h bit 2 to output mode) =0 PIO2 function (set register 57h bit 2 to determine input or output mode) 1 PIO1/NOWS# pin selector =1 NOWS# function (set register 57h bit 1 to input mode) =0 PIO1 function (set register 57h bit 1 to determine input or output mode) 0 enable CPU clock change request protocol Note: for hardware doze mode, bit 5 must be 0 SeeAlso: #P0135,#P0147,#P0154,#P0159,#P0174 Bitfields for OPTi 82C463MV CPU frequency (register 67h): Bit(s) Description (Table P0174) 7 CPU clock control during suspend =1 dynamic CPU (in suspend-mode, bits 2-0 select the CPU clock) =0 static CPU (in suspend-mode, 82C463MV stops the CPU clock) 6 refresh control =1 slow refresh (128 ms) =0 normal refresh (15 ms for normal operation, 30 ms for suspend mode) 5 PMU global enabler 4 reserved (1) 3 reserved (0) 2-0 CPU clock frequency 000 CPUCLK/1 001 CPUCLK/2 010 CPUCLK/4 101 CPUCLK/3 else reserved SeeAlso: #P0135 Bitfields for OPTi 82C463MV timer clock source (register 68h): Bit(s) Description (Table P0175) 7-6 R_TIMER clock source selector 00 SQW0 01 SQW1 10 SQW2 11 SQW3 5-4 IDLE_TIMER clock source selector (see bits 7-6) 3-2 resume recovery time if register 40h bit 6 =1 00 8 ms 01 32 ms 10 128 ms 11 256 ms if register 40h bit 6 =0 00 2 ms 01 8 ms 10 32 ms 11 64 ms 1 enable PPWR bit 1 suspend auto toggle (see also #P0156) 0 enable PPWR bit 0 suspend auto toggle (see also #P0156) Note: bits 1 and 0 are not influenced by mask bits 5 and 4 of register 54h SeeAlso: #P0135,#P0146 Bitfields for OPTi 82C463MV resume IRQ selects (register 6Ah): Bit Description (Table P0176) 7 enable EPMI2 (resume on a rising edge) 6 enable EPMI1 (resume on a rising edge) 5 enable IRQ8 (resume on a falling edge) 4 enable IRQ7 (resume on a rising edge) 3 enable IRQ5 (resume on a rising edge) 2 enable IRQ4 (resume on a rising edge) 1 enable IRQ3 (resume on a rising edge) 0 enable IRQ1 (resume on a rising edge) SeeAlso: #P0135 Bitfields for OPTi 82C463MV resume sources (register 6Bh): Bit(s) Description (Table P0177) 7 refresh pulse width during sequencer operation =1 6 AT clocks =0 4 AT clocks 6-3 reserved (0) 2-0 resume sources (read-only) 001 RI 010 INTR (as selected in register 6Ah) 100 SUSP/RSM pin else reserved SeeAlso: #P0135,#P0176 ----------P00220024-------------------------- PORT 0022-0024 - OPTi 82C493 System Controller (SYSC) - CONFIGURATION REGISTERS Desc: The OPTi 486SXWB contains three chips and is designed for systems running at 20, 25 and 33MHz. The chipset includes an 82C493 System Controller (SYSC), the 82C392 Data Buffer Controller, and the 82C206 Integrated peripheral Controller (IPC). Note: every access to PORT 0024h must be preceded by a write to PORT 0022h, even if the same register is being accessed a second time SeeAlso: PORT 0022h"82C206" 0022 ?W configuration register index (see #P0178) 0024 RW configuration register data (Table P0178) Values for OPTi 82C493 System Controller configuration register index: 20h Control Register 1 (see #P0179) 21h Control Register 2 (see #P0180) 22h Shadow RAM Control Register 1 (see #P0181) 23h Shadow RAM Control Register 2 (see #P0182) 24h DRAM Control Register 1 (see #P0183) 25h DRAM Control Register 2 (see #P0184) 26h Shadow RAM Control Register 3 (see #P0185) 27h Control Register 3 (see #P0186) 28h Non-cachable Block 1 Register 1 (see #P0187) 29h Non-cachable Block 1 Register 2 (see #P0188) 2Ah Non-cachable Block 2 Register 1 (see #P0187) 2Bh Non-cachable Block 2 Register 2 (see #P0188) Bitfields for OPTi-82C493 Control Register 1: Bit(s) Description (Table P0179) 7-6 Revision of 82C493 (readonly) (default=01) 5 Burst wait state control 1 = Secondary cache read hit cycle is 3-2-2-2 or 2-2-2-2 0 = Secondary cache read hit cycle is 3-1-1-1 or 2-1-1-1 (default) (if bit 5 is set to 1, bit 4 must be set to 0) 4 Cache memory data buffer output enable control 0 = disable (default) 1 = enable (must be disabled for frequency <= 33Mhz) 3 Single Address Latch Enable (ALE) 0 = disable (default) 1 = enable (if enabled, SYSC will activate single ALE rather than multiples during bus conversion cycles) 2 enable Extra AT Cycle Wait State (default is 0 = disabled) 1 Emulation keyboard Reset Control 0 = disable (default) 1 = enable Note: This bit must be enabled in BIOS default value; enabling this bit requires HALT instruction to be executed before SYSC generates processor reset (CPURST) 0 enable Alternative Fast Reset (default is 0 = disabled) SeeAlso: #P0180,#P0186 Bitfields for OPTi-82C493 Control Register 2: Bit(s) Description (Table P0180) 7 Master Mode Byte Swap Enable 0 = disable (default) 1 = enable 6 Emulation Keyboard Reset Delay Control 0 = Generate reset pulse 2us later (default) 1 = Generate reset pulse immediately 5 disable Parity Check (default is 0 = enabled) 4 Cache Enable 0 = Cache disabled and DRAM burst mode enabled (default) 1 = Cache enabled and DRAM burst mode disabled 3-2 Cache Size 00 64KB (default) 01 128KB 10 256KB 11 512KB 1 Secondary Cache Read Burst Cycles Control 0 = 3-1-1-1 cycle (default) 1 = 2-1-1-1 cycle 0 Cache Write Wait State Control 0 = 1 wait state (default) 1 = 0 wait state SeeAlso: #P0179,#P0186 Bitfields for OPTi-82C493 Shadow RAM Control Register 1: Bit(s) Description (Table P0181) 7 ROM(F0000h - FFFFFh) Enable 0 = read/write on write-protected DRAM 1 = read from ROM, write to DRAM (default) 6 Shadow RAM at D0000h - EFFFFh Area 0 = disable (default) 1 = enable 5 Shadow RAM at E0000h - EFFFFh Area 0 = disable shadow RAM (default) E0000h - EFFFFh ROM is defaulted to reside on XD bus 1 = enable shadow RAM 4 enable write-protect for Shadow RAM at D0000h - DFFFFh Area 0 = disable (default) 1 = enable 3 enable write-protect for Shadow RAM at E0000h - EFFFFh Area 0 = disable (default) 1 = enable 2 Hidden refresh enable (with holding CPU) (Hidden refresh must be disabled if 4Mx1 or 1M x4 bit DRAM are used) 1 = disable (default) 0 = enable 1 unused 0 enable Slow Refresh (four times slower than normal refresh) (default is 0 = disable) SeeAlso: #P0182 Bitfields for OPTi-82C493 Shadow RAM Control Register 2: Bit(s) Description (Table P0182) 7 enable Shadow RAM at EC000h - EFFFFh area 6 enable Shadow RAM at E8000h - EBFFFh area 5 enable Shadow RAM at E4000h - E7FFFh area 4 enable Shadow RAM at E0000h - E3FFFh area 3 enable Shadow RAM at DC000h - DFFFFh area 2 enable Shadow RAM at D8000h - DBFFFh area 1 enable Shadow RAM at D4000h - D7FFFh area 0 enable Shadow RAM at D0000h - D3FFFh area Note: the default is disabled (0) for all areas Bitfields for OPTi-82C493 DRAM Control Register 1: Bit(s) Description (Table P0183) 7 DRAM size 0 = 256K DRAM mode 1 = 1M and 4M DRAM mode 6-4 DRAM types used for bank0 and bank1 bits 7-4 Bank0 Bank1 0000 256K x 0001 256K 256K 0010 256K 1M 0011 x x 01xx x x 1000 1M x (default) 1001 1M 1M 1010 1M 4M 1011 4M 1M 1100 4M x 1101 4M 4M 111x x x 3 unused 2-0 DRAM types used for bank2 and bank3 bits 7,2-0 Bank2 Bank3 x000 1M x x001 1M 1M x010 x x x011 4M 1M x100 4M x x101 4M 4M x11x x x (default) SeeAlso: #P0184 Bitfields for OPTi-82C493 DRAM Control Register 2: Bit(s) Description (Table P0184) 7-6 Read cycle additional wait states 00 not used 01 = 0 10 = 1 11 = 2 (default) 5-4 Write cycle additional wait states 00 = 0 01 = 1 10 = 2 11 = 3 (default) 3 Fast decode enable 0 = disable fast decode. DRAM base wait states not changed (default) 1 = enable fast decode. DRAM base wait state is decreased by 1 Note: This function may be enabled in 20/25Mhz operation to speed up DRAM access. If bit 4 of index register 21h (cache enable bit) is enabled, this bit is automatically disabled--even if set to 1 2 unused 1-0 ATCLK selection 00 ATCLK = CLKI/6 (default) 01 ATCLK = CLKI/4 (default) 10 ATCLK = CLKI/3 11 ATCLK = CLK2I/5 (CLKI * 2 /5) Note: bit 0 will reflect the BCLKS (pin 142) status and bit 1 will be set to 0 when 82C493 is reset. SeeAlso: #P0183,#P0185 Bitfields for OPTi-82C493 Shadow RAM Control Register 3: Bit(s) Description (Table P0185) 7 unused 6 Shadow RAM copy enable for address C0000h - CFFFFh 0 = Read/write at AT bus (default) 1 = Read from AT bus and write into shadow RAM 5 Shadow write protect at address C0000h - CFFFFh 0 = Write protect disable (default) 1 = Write protect enable 4 enable Shadow RAM at C0000h - CFFFFh 3 enable Shadow RAM at CC000h - CFFFFh 2 enable Shadow RAM at C8000h - CBFFFh 1 enable Shadow RAM at C4000h - C7FFFh 0 enable Shadow RAM at C0000h - C3FFFh Note: the default is disabled (0) for bits 4-0 SeeAlso: #P0183,#P0184 Bitfields for OPTi-82C493 Control Register 3: Bit(s) Description (Table P0186) 7 enable NCA# pin to low state (default is 1 = enabled) 6-5 unused 4 Video BIOS at C0000h - C8000h non-cacheable 0 = cacheable 1 = non-cacheable (default) 3-0 Cacheable address range for local memory 0000 0 - 64MB 0001 0 - 4MB (default) 0010 0 - 8MB 0011 0 - 12MB 0100 0 - 16MB 0101 0 - 20MB 0110 0 - 24MB 0111 0 - 28MB 1000 0 - 32MB 1001 0 - 36MB 1010 0 - 40MB 1011 0 - 44MB 1100 0 - 48MB 1101 0 - 52MB 1110 0 - 56MB 1111 0 - 60MB Note: If total memory is 1MB or 2MB the cacheable range is 0-1 MB or 0-2 MB and independent of the value of bits 3-0 SeeAlso: #P0179,#P0180 Bitfields for OPTi-82C493 Non-cacheable Block Register 1: Bit(s) Description (Table P0187) 7-5 Size of non-cachable memory block 000 64K 001 128K 010 256K 011 512K 1xx disabled (default) 4-2 unused 1-0 Address bits 25 and 24 of non-cachable memory block (default = 00) Note: this register is used together with configuration register 29h (non-cacheable block 1) or register 2Bh (block 2) (see #P0188) to define a non-cacheable block. The starting address must be a multiple of the block size SeeAlso: #P0178,#P0188 Bitfields for OPTi-82C493 Non-cacheable Block Register 2: Bit(s) Description (Table P0188) 7-0 Address bits 23-16 of non-cachable memory block (default = 0001xxxx) Note: the block address is forced to be a multiple of the block size by ignoring the appropriate number of the least-significant bits SeeAlso: #P0178,#P0187 ----------P00220024-------------------------- PORT 0022-0024 - OPTi "Viper" (82C557) CHIPSET - SYSTEM CONTROL REGISTERS Note: every access to PORT 0024h must be preceded by a write to PORT 0022h, even if the same register is being accessed a second time SeeAlso: PORT 0022h"82C206" 0022 ?W index for accesses to data port (see #P0189) 0023 RW DMA clock select (see #P0087) 0024 RW chip set data (Table P0189) Values for OPTi "Viper" (82C557) system control registers: 00h Byte Merge/Prefetch and Sony Cache Module Control register (see #P0190) 00h Compatible DRAM Configuration register 1 (see #P0191) (refer to note) 01h DRAM Control register 1 (see #P0192) 02h Cache Control register 1 (see #P0193) 03h Cache Control register 2 (see #P0194) 04h Shadow RAM Control register 1 (see #P0195) 05h Shadow RAM Control register 2 (see #P0197) 06h Shadow RAM Control register 3 (see #P0198) 07h Tag Test register (see #P0199) 08h CPU Cache Control register (see #P0200) 09h System Memory Function register (see #P0201) 0Ah DRAM Hole A Address Decode register 1 (see #P0202) 0Bh DRAM Hole B Address Decode register 2 (see #P0203) 0Ch Extended DMA register (see #P0204) 0Dh Clock Control register (see #P0205) 0Eh Cycle Control register 1 (see #P0206) 0Fh Cycle Control register 2 (see #P0207) 10h Miscellaneous Control register 1 (see #P0208) 11h Miscellaneous Control register 2 (see #P0209) 12h Refresh Control register (see #P0210) 13h Memory Decode Control register 1 (see #P0211) 14h Memory Decode Control register 2 (see #P0213) 15h PCI Cycle Control register 1 (see #P0214) 16h Dirty/Tag RAM Control register (see #P0215) 17h PCI Cycle Control register 2 (see #P0216) 18h Tristate Control register (see #P0217) 19h Memory Decode Control register 3 (see #P0218) 1Ah-1Fh reserved Note: Byte Merge/Prefetch and Sony Cache Module Control register is accessed through register 00h when bit 7 of register 13h is set, otherwise Compatible DRAM Configuration register 1 is accessed as register 00h reserved registers 1Ah-1Fh must be written to 0 SeeAlso: #P0121,#P0211 Bitfields for OPTi "Viper" Byte Merge / Sony Cache Module Control register: Bit(s) Description (Table P0190) 7 enable pipelining of single CPU cycles to memory 6 enable video memory byte/word read prefetch. Enables the prefetching of bytes/words from PCI video memory to the CPU 5 enable Sony SONIC-2WP support. If set, the ensure that the L2 cache has been disabled (register 02h bits 3-2) 4 enable byte/word merge support 3 enable byte/word merging with CPU pipelining (NA# generation) support 2-1 time-out counter for byte/word merge. Determines the maximum time difference between two consecutive PCI bye/word writes to allow merging 00 4 CPU CLKs 01 8 CPU CLKs 10 12 CPU CLKs 11 16 CPU CLKs 0 enable internal hold requests to be blocked while performing byte merge SeeAlso: #P0189 Bitfields for OPTi "Viper" Compatible DRAM Configuration register 1: Bit(s) Description (Table P0191) 7 enable pipelining of single CPU cycles to memory 6 second bank SIMM selection. SIMMs need to be single sided 0 single sided SIMM not installed in bank 0 1 single sided SIMM installed in bank 0 5 first bank SIMM selection. SIMMs need to be single sided 0 single sided SIMM not installed in bank 0 1 single sided SIMM installed in bank 0 4-0 banks 0 thru 3 DRAM configuration (val) Bank0 Bank1 Bank2 Bank3 00000 256K 256KB - - 00001 512K 512K - - 00010 1M 1M - - 00011 2M 2M - - 00100 4M 4M - - 00101 8M 8M - - 00110 256K 256K 256K 256K 00111 256K 256K 512K 512K 01000 512K 512K 512K 512K 01001 256K 256K 1M 1M 01010 512K 512K 1M 1M 01011 1M 1M 1M 1M 01100 256K 256K 2M 2M 01101 512K 512K 2M 2M 01110 1M 1M 2M 2M 01111 2M 2M 2M 2M 10000 256K 256K 4M 4M 10001 512K 512K 4M 4M 10010 1M 1M 4M 4M 10011 2M 2M 4M 4M 10100 4M 4M 4M 4M 10101 256K 256K 8M 8M 10110 512K 512K 8M 8M 10111 1M 1M 8M 8M 11000 2M 2M 8M 8M 11001 4M 4M 8M 8M 11010 8M 8M 8M 8M Note: these settings maintain backward compatibility with the "Python" (82C546/82C547) chipset, and they do not allow for much flexibility SeeAlso: #P0189 Bitfields for OPTi "Viper" (82C557) DRAM Control register 1: Bit(s) Description (Table P0192) 7 row address hold after RAS# active in CLKs 0 2 CLKs 1 1 CLK 6 RAS# active/inactive on entering master mode 0 normal page mode when starting a master cycle, RAS# will remain 1 RAS# inactive when starting a master cycle 5-4 RAS pulse width used during refresh 00 7 CLKs 01 6 CLKs 10 5 CLKs 11 4 CLKs 3 CAS pulse width during reads 0 3 CLKs 1 2 CLKs 2 CAS pulse width during writes 0 3 CLKs 1 2 CLKs 1-0 RAS precharge time 00 6 CLKs 01 5 CLKs 10 4 CLKs 11 3 CLKs SeeAlso: #P0189,#P0193,#P0219 Bitfields for OPTi "Viper" (82C557) Cache Control register 1: Bit(s) Description (Table P0193) 7-6 cache size selection; determines size of the L2 cache, along with register 0Fh bit 0. When set, it works as a *16 multiplier 00 (Viper) 64K (1M when register 0Fh bit 0 set) (Vendetta) reserved 01 (Viper) 128K (2M when register 0Fh bit 0 set) (Vendetta) reserved 10 256K (reserved when register 0Fh bit 0 set) 11 512K (reserved when register 0Fh bit 0 set) 5-4 cache write policy; determines the write policy for the L2 cache 00 L2 cache write-through 01 Adaptive Write-back Mode 1 10 Adaptive Write-back Mode 2 11 L2 cache write-back 3-2 cache mode select; determines the operating mode of the L2 cache 00 disable 01 Test Mode 1, External Tag Write (Tag data write-through reg. 07h) 10 Test Mode 2, External Tag Read (Tag data read from register 07h) 11 enable L2 cache 1 enable DRAM posted write 0 CAS precharge time 0 2 CLKs 1 1 CLK SeeAlso: #P0189,#P0199,#P0207,#P0194,#P0219 Bitfields for OPTi "Viper" (82C557) Cache Control register 2: Bit(s) Description (Table P0194) 7-6 L2 cache write burst mode timings 00 X-4-4-4 01 X-3-3-3 10 X-2-2-2 11 X-1-1-1 5-4 L2 cache write lead-off cycle timings 00 5-X-X-X 01 4-X-X-X 10 3-X-X-X 11 2-X-X-X 3-2 L2 cache read burst mode timings 00 X-4-4-4 01 X-3-3-3 10 X-2-2-2 11 X-1-1-1 1-0 L2 cache read lead-off cycle timings 00 5-X-X-X 01 4-X-X-X 10 3-X-X-X 11 2-X-X-X Note: SRAM double bank implementation does not support lead-off timing SeeAlso: #P0189,#P0193,#P0219 Bitfields for OPTi "Viper"/"Vendetta" Shadow RAM Control register 1: Bit(s) Description (Table P0195) 7-6 CC000-CFFFF read/write control; determines the R/W control for these segments of the shadow RAM (see #P0196) 5-4 C8000-CBFFF read/write control; determines the R/W control for these segments of the shadow RAM (see #P0196) 3 enable synchronous SRAM pipelined read cycle 1-1-1-1 2 E0000-EFFFF range selection 0 area will always be non-cacheable 1 are will be treated like the F0000h BIOS area 1-0 C0000-C7FFF read/write control; determines the R/W control for these segments of the shadow RAM (see #P0196) Note: bit 3 will act only when register 11h bit 3 and register 03h bits 3-2 are all set when bit 2 is set, register 06h bits 3-0 should be set identically SeeAlso: #P0189,#P0197,#P0219 (Table P0196) Values for OPTi "Viper"/"Vendetta" Shadow RAM Control setting: 00 read/write PCI bus 01 read from DRAM/write to PCI 10 read from PCI/write to DRAM 11 read from/write to DRAM SeeAlso: #P0195,#P0197,#P0198,#P0219 Bitfields for OPTi "Viper"/"Vendetta" Shadow RAM Control register 2: Bit(s) Description (Table P0197) 7-6 DC000-DFFFF read/write control; determines the R/W control for these segments of the shadow RAM (see #P0196) 5-4 D8000-DBFFF read/write control; determines the R/W control for these segments of the shadow RAM (see #P0196) 3-2 D4000-D7FFF read/write control; determines the R/W control for these segments of the shadow RAM (see #P0196) 1-0 D0000-D3FFF read/write control; determines the R/W control for these segments of the shadow RAM (see #P0196) SeeAlso: #P0189,#P0195,#P0198,#P0219 Bitfields for OPTi "Viper"/"Vendetta" Shadow RAM Control register 3: Bit(s) Description (Table P0198) 7 DRAM hole in system memory from 80000-9FFFF; gives the user the option to have some other device in this address range instead of system memory. When set, the SYSC will not start the system DRAM controller for accesses to this particular address range 0 no memory hole 1 enable memory hole 6 wait state addition for PCI master snooping 0 do not add a wait state 1 add a wait state for the cycle access to finish and then do snooping 5 enable C0000-C7FFF cacheability in L1 and L2 cache memory 4 enable F0000-FFFFF cacheability in L1 and L2 cache memory 3-2 F0000-FFFFF read/write control; determines the R/W control for these segments of the shadow RAM (see #P0196) 1-0 E0000-EFFFF read/write control; determines the R/W control for these segments of the shadow RAM (see #P0196) Note: L1 cacheability can be disabled thru register 08h bit 0 If register 04h bit 2 is set, then F0000-FFFFF and E0000-EFFFF R/W control settings should have similar values SeeAlso: #P0189,#P0197,#P0219 Bitfields for OPTi "Viper"/"Vendetta" Tag Test register: Bit(s) Description (Table P0199) 7-0 Tag Test register; when in cache Test Mode, data is read from/written to this register SeeAlso: #P0189,#P0193,#P0219 Bitfields for OPTi "Viper"/"Vendetta" CPU Cache Control register: Bit(s) Description (Table P0200) 7 L2 cache single/double bank select 0 (Viper) two banks of L2 cache (Vendetta) reserved 1 single bank of L2 cache (non-interleaved) 6 enable snoop filtering for bus masters 5 CPU HITM# pin sample timing 0 (Viper) delay one clock, therefore HITM# sampled on the third rising edge of LCLK after EADS# has been asserted (Vendetta) reserved 1 do not delay, therefore HITM# sampled on the second rising edge 4 enable parity checking 3 Tag/Dirty RAM implementation 0 (Viper) Tag and Dirty are on separate chips (Vendetta) reserved 1 Tag and Dirty are on the same chip