OPCODE LIST Release 61 Last change 16jul00 ------------------ OPCODE.LST ---------------------------- This is DOC 'bout undocument command and document command of any last processors. And 'bout some registers and Chips specific stuffs. ----------------------------------------------------------- (C) (P) Potemkin's Hackers Group 1994...1999 ----------------------------------------------------------- Revision 4.51 15 Oct 1999 ----------------------------------------------------------- Latest versions available on Web: http://www.chat.ru/~phg Our contact E-mail: avp@gdev.msk.ru ICQ UIN: 20570214 ------------------------------------------------------------ [New In revision 4.50] o AMD 3DNow! Extentions and Athlon CPU o Update CPUID features summary o Update OPCODE tables o Update CPU revisions ------------------------------------------------------------- --------------------------------------------------- OPCODE AAA - ASCII adjust AX after addition CPU: 8086+ Type of Instruction: User Instruction: AAA ; (no operands) Description: IF ((( AL and 0FH ) > 9 ) or (AF==1) THEN { IF CPU<286 THEN { AL <- AL+6 } ELSE { AX <- AX+6 } AH <- AH+1 CF <- 1 AF <- 1 } ELSE { CF <- 0 AF <- 0 } AL <- AL and 0Fh Note: This istruction incorrectly documented in Intel's materials. See description field. Flags Affected: AF,CF (modified) OF,SF,ZF,PF (undefined) Faults: RM PM V86 VME None CPU mode: RM,PM,VM,SMM +++++++++++++++++++++++ Physical Form: COP (Code of Operation) : 37H Clocks: AAA 8086: 4 8088: 4 80186: 8 80286: 3 80386: 4 i486: 3 Pentium: 3 Cx486SLC: 4 Cx486DX: 4 IBM 486BL3X: 4 UMC U5S: 1 --------------------------------------------------- OPCODE AAD - ASCII adjust AX before Division CPU: 8086+ Type of Instruction: User Instruction: AAD basen Description: AL <- (AH*basen) + AL AH <- 0 Flags Affected: SF,ZF,PF (modified) OF,AF,CF (undefined) Faults: RM PM V86 VME SMM None CPU mode: RM,PM,VM,SMM Note: AAD without operands means AAD with operand 0AH. Note: NECs understand only AAD 0AH form. +++++++++++++++++++++++ Physical Form: AAD imm8 COP (Code of Operation) : D5H imm8 Clocks: AAD 0AH 8086: 60 80186: 15 80286: 14 80386: 19 i486: 14 Pentium: 10 Cx486SLC: 4 Cx486DX: 4 IBM 486BL3X: 15 UMC U5S: 11 --------------------------------------------------- OPCODE AAM - ASCII adjust AX after Multiply CPU: 8086+ Type of Instruction: User Instruction: AAM basen Description: AH <- AL / basen AL <- AL MOD basen Flags Affected: SF,ZF,PF (modified) OF,AF,CF (undefined) Faults: RM PM V86 VME SMM None CPU mode: RM,PM,VM,SMM Note: AAM without operands means AAM with operand 0AH. WARNING: NECs understand only AAM 0Ah form. +++++++++++++++++++++++ Physical Form: AAM imm8 COP (Code of Operation) : D4H imm8 Clocks: AAM 0AH 8086: 83 80186: 19 80286: 16 80386: 17 i486: 15 Pentium: 18 Cx486SLC: 16 Cx486DX: 16 IBM 486BL3X: 17 UMC U5S: 12 --------------------------------------------------- OPCODE ADD4S - Addition for packed BCD strings CPU: all NECs V-series Type of Instruction: User Instruction: ADD4S Description: BCD STRING (ADDRESS=ES:DI,LENGTH=CL) <- BCD STRING (ADDRESS=DS:SI,LENGTH=CL) + BCD STRING (ADDRESS=ES:DI,LENGTH=CL); Note: si,di, other registers not changed Flags Affected: OF,CF,ZF ;; ZF set if both strings are zeros. ;; CF,OF set as result of operation with most ;; signification BCDs. CPU mode: RM +++++++++++++++++++++++ Physical Form: ADD4S COP (Code of Operation) : 0FH 20H Clocks: ADD4S NEC V20: ~19*(CL/2)+7 ----------------------------------------------------------------- ADDPS - Packed Single-FP Add CPU: Pentium III+ (KNI/MMX2) Type of instruction: User Instruction: ADDPS dest,src Description: dest[<0>] = dest[<0>] + src[<0>]; dest[<1>] = dest[<1>] + src[<1>]; dest[<2>] = dest[<2>] + src[<2>]; dest[<3>] = dest[<3>] + src[<3>]; addition is F.P. <0> = 31..0 <2> = 95..64 <1> = 63..32 <3> = 127..96 Physical Form and Timing: ADDPS xmm1,xmm2/m128 ---- 0F 58 /r ---- 2 ----------------------------------------------------------------- ADDSS - Scalar Single-FP Add CPU: Pentium III+ (KNI/MMX2) Type of instruction: User Instruction: ADDSS dest,src Description: dest[<0>] = dest[<0>] + src[<0>]; addition is F.P. <0> = 31..0 <2> = 95..64 <1> = 63..32 <3> = 127..96 Physical Form and Timing: ADDSS xmm1,xmm2/m32 ---- F3 0F 58 /r ---- 1 ----------------------------------------------------------------- ANDNPS - Bit-wise Logical And Not For Single-FP CPU: Pentium III+ (KNI/MMX2) Type of instruction: User Instruction: ANDNPS dest,src Description: dest = NOT( dest AND src ); // Bitwize Physical Form and Timing: ANDNPS xmm1,xmm2/m128 ---- 0F 55 /r ---- 2 ----------------------------------------------------------------- ANDPS - Bit-wise Logical And For Single-FP CPU: Pentium III+ (KNI/MMX2) Type of instruction: User Instruction: ANDPS dest,src Description: dest = dest AND src; // Bitwize Physical Form and Timing: ANDPS xmm1,xmm2/m128 ---- 0F 54 /r ---- 2 --------------------------------------------------- OPCODE BOUND - Chack Array Index Against Bounds CPU: 80186+,NECs Type of Instruction: User - HLL support Instruction: BOUND index,bound_array Description: IF (index < (opsize ptr [bound_array])) OR (index > (opsize ptr [bound_array+opsize])) THEN INT 5; Flags Affected: No Flags Affected CPU mode: RM,PM,VM,SMM Faults: RM PM V86 VME SMM #GP(0) if result is nonwritable seg. #GP(0) illegal memory operand in CS..GS (exc. SS) #SS(0) illegal memory operand in SS #PF #PF #UD #UD #UD if 2nd operand is register #13 if any part of operand lie outside of 0..FFFFh #AC #AC if CPL=3 and enable AC. Note: (186s&NECs) saved CS:IP BOUND interrupt as pointer to following instruction that self. (286+) saved as pointer to BOUND instruction. +++++++++++++++++++++++ Physical Form: BOUND reg16,mem32 BOUND reg32,mem64 COP (Code of Operation) : 62H Postbyte Note: for 32bit op. add Pfix 66h if in 16bit mode Clocks: BOUND reg16,mem16 In Range Out Range 80186: 33-35 80286: 13 int+13 80386: 10 i486: 7 Pentium: 8 int+32 Cx486SLC: 11 int+11 Cx486DX: 11 int+11 --------------------------------------------------- OPCODE BRKCS - Break with Contex Switch CPU: NEC V25,V35,V25 Plus,V35 Plus,V25 Software Guard Type of Instruction: System Instruction: BRKCS bank Description: Perform a High-Speed Software Interrupt with contex-switch to register bank indicated by the lower 3-bits of 'bank'. Info: NEC V25/V35/V25 Plus/V35 Plus Bank System This Chips have 8 32bytes register banks, which placed in Internal chip RAM by addresses: xxE00h..xxE1Fh Bank 0 xxE20h..xxE3Fh Bank 1 ......... xxEC0h..xxEDFh Bank 6 xxEE0h..xxEFFh Bank 7 xxF00h..xxFFFh Special Functions Register Where xx is Value of IDB register. IBD is Byte Register contained Internal data area base IBD addresses is FFFFFh and xxFFFh where xx is data in IBD. Format of Bank: +0 Reserved +2 Vector PC +4 Save PSW +6 Save PC +8 DS0 ;DS +A SS ;SS +C PS ;CS +E DS1 ;ES +10 IY ;DI +11 IX ;SI +14 BP ;BP +16 SP ;SP +18 BW ;BX +1A DW ;DX +1C CW ;CX +1E AW ;AX Format of V25 etc. PSW (FLAGS): Bit Description 15 1 14 RB2 \ 13 RB1 > Current Bank Number 12 RB0 / 11 V ;OF 10 DIR ;DF 9 IE ;IF 8 BRK ;TF 7 S ;SF 6 Z ;ZF 5 F1 General Purpose user flag #1 (accessed by Flag Special Function Register) 4 AC ;AF 3 F0 General purpose user flag #0 (accessed by Flag Special Function Register) 2 P ;PF 1 BRKI I/O Trap Enable Flag 0 CY ;CF Flags Affected: None CPU mode: RM +++++++++++++++++++++++ Physical Form: BRKCS reg16 COP (Code of Operation) : 0Fh 2Dh <1111 1RRR> Clocks: 15 --------------------------------------------------- OPCODE BRKEM - Break for Emulation CPU: NEC/Sony V20/V30/V40/V50 Type of Instruction: System Instruction: BRKEM intnum Description: PUSH FLAGS PUSH CS PUSH IP MOV CS,0:[intnum*4+2] MOV IP,0:[intnum*4] MD <- 0; // Enable 8080 emulation Note: BRKEM instruction do software interrupt and then New CS,IP loaded it switch to 8080 mode i.e. CPU will execute 8080 code. Mapping Table of Registers in 8080 Mode 8080 Md. A B C D E H L SP PC F native. AL CH CL DH DL BH BL BP IP FLAGS(low) For Return of 8080 mode use CALLN instruction. Note: I.e. 8080 addressing only 64KB then "Real Address" is CS*16+PC Flags Affected: MD CPU mode: RM +++++++++++++++++++++++ Physical Form: BRKEM imm8 COP (Code of Operation) : 0FH FFH imm8 Clocks: BRKEM imm8 NEC V20: 38 --------------------------------------------------- OPCODE BRKN - Break to Native Mode CPU: NEC (V25/V35) Software Guard only Type of Instruction: System Instruction: BRKN int_vector Description: [sp-1,sp-2] <- PSW ; PSW EQU FLAGS [sp-3,sp-4] <- PS ; PS EQU CS [sp-5,sp-6] <- PC ; PC EQU IP SP <- SP -6 IE <- 0 BRK <- 0 MD <- 1 PC <- [int_vector*4 +0,+1] PS <- [int_vector*4 +2,+3] Note: The BRKN instruction switches operations in Native Mode from Security Mode via Interrupt call. In Normal Mode Instruction executed as mPD70320/70322 (V25) operation mode. Flags Affected: None CPU mode: RM +++++++++++++++++++++++ Physical Form: BRKN imm8 COP (Code of Operation) : 63h imm8 Clocks: 56+10T [44+10T] --------------------------------------------------- OPCODE BRKS - Break to Security Mode CPU: NEC (V25/V35) Software Guard only Type of Instruction: System Instruction: BRKS int_vector Description: [sp-1,sp-2] <- PSW ; PSW EQU FLAGS [sp-3,sp-4] <- PS ; PS EQU CS [sp-5,sp-6] <- PC ; PC EQU IP SP <- SP -6 IE <- 0 BRK <- 0 MD <- 0 PC <- [int_vector*4 +0,+1] PS <- [int_vector*4 +2,+3] Note: The BRKS instruction switches operations in Security Mode via Interrupt call. In Security Mode the fetched operation code is executed after conversion in accordance with build-in translation table Flags Affected: None CPU mode: RM +++++++++++++++++++++++ Physical Form: BRKS imm8 COP (Code of Operation) : F1h imm8 Clocks: 56+10T [44+10T] --------------------------------------------------- OPCODE BRKXA - Break to Expansion Address CPU: NEC V33/V53 only Type of Instruction: System Instruction: BRKXA int_vector Description: [sp-1,sp-2] <- PSW ; PSW EQU FLAGS [sp-3,sp-4] <- PS ; PS EQU CS [sp-5,sp-6] <- PC ; PC EQU IP SP <- SP -6 IE <- 0 BRK <- 0 MD <- 0 PC <- [int_vector*4 +0,+1] PS <- [int_vector*4 +2,+3] Enter Expansion Address Mode. Note: In NEC V53 Memory Space dividing into 1024 16K pages. The programming model is Same as in Normal mode. Mechanism is: 20 bit Logical Address: 19..14 Page Num 13..0 Offset page Num convertin by internal table to 23..14 Page Base tHE pHYSICAL ADDRESS is both Base and Offset. Address Expansion Registers: logical Address A19..A14 I/O Address 0 FF00h 1 FF02h ... ... 63 FF7Eh Register XAM aliased with port # FF80h indicated current mode of operation. Format of XAM register (READ ONLY): 15..1 reserved 0 XA Flag, if=1 then in XA mode. Format of V53 PSW: 15..12 1 11 V 10 DIR 9 IE 8 BRK 7 S 6 Z 5 0 4 AC 3 0 2 P 1 1 0 CY Flags Affected: None CPU mode: RM +++++++++++++++++++++++ Physical Form: BRKXA imm8 COP (Code of Operation) : 0Fh E0h imm8 Clocks: 12 --------------------------------------------------- OPCODE BSWAP - Bytes Swap CPU: I486 + Type of Instruction: User Instruction: BSWAP dwordr Description: XCHG BYTE dwordr[31:24],dwordr[7:0] XCHG BYTE dwordr[23:16],dwordr[15:8] ; Need Good Picture to Show It Notes: This instruction used for converting big-endian (Intel) format to little-endian (Motorolla etc.) format. Flags Affected: None CPU mode: RM,PM,VM,SMM Physical Form: BSWAP r32 COP (Code of Operation): 0FH 11001rrr (For 32bit segment) Clocks: Cyrix Cx486SLC : 4 i486 : 1 Pentium : 1 Cyrix Cx486DX : 4 UMC U5S : 2 IBM 486BL3X : 9 --------------------------------------------------- OPCODE BTCLR - Bit Test, If it True Clear and Branch CPU: NEC V25,V35,V25 Plus,V35 Plus,V25 Software Guard Type of Instruction: User Instruction: BTCLR var,bitnumber,Short_Label Description: IF BIT(bitnumber OF var) =1 THEN { PC <- PC + ext - disp8; BIT(bitnumber OF var) <-0 } Flags Affected: None CPU mode: RM +++++++++++++++++++++++ Physical Form: BTCLR reg/mem8,imm3, short_label COP (Code of Operation) : 0Fh 9Ch PostByte imm3 Short_Label (Total=5 bytes) Clocks: 29 --------------------------------------------------- OPCODE CALLN - Call Native Mode Routine CPU: NEC/Sony V20/V30 etc Type of Instruction: System Instruction: CALLN intnum Description: CALLN instruction call (interrupt service in Native Mode) from 8080 emulation mode: PUSH FLAGS PUSH CS PUSH IP IF <- 0 TF <- 0 MD <- 1 MOV CS,0:[intnum*4+2] MOV IP,0:[intnum*4] Flags Affected: IF,TF,MD CPU mode: 8080 Emulation +++++++++++++++++++++++ Physical Form: CALLN imm8 COP (Code of Operation) : EDH EDH imm8 Clocks: NEC V20/V30: 38-58 --------------------------------------------------- OPCODE CLEAR1 - Clear one bit CPU: NEC/Sony all V-series. Type of Instruction: User Instruction: CLEAR1 dest,bitnumb Description: BIT bitnumb OF dest <- 0; Flags Affected: None CPU mode: RM +++++++++++++++++++++++ Physical Form: CLEAR1 reg/mem8,CL COP (Code of Operation) : 0FH 12H Postbyte Physical Form: CLEAR1 reg/mem8,imm8 COP (Code of Operation) : 0FH 1AH Postbyte imm8 Physical Form: CLEAR1 reg/mem16,CL COP (Code of Operation) : 0FH 13H Postbyte Physical Form: CLEAR1 reg/mem16,imm8 COP (Code of Operation) : 0FH 1BH Postbyte imm8 Clocks: CLEAR1 r/m8,CL r/m8,i8 r/m16,CL r/m16,i8 NEC V20: 5/14 6/15 5/14 6/15 --------------------------------------------------- OPCODE CMOVcc - Conditional Move CPU: P6 Type of Instruction: User Instruction: CMOVcc dest,sorc Description: IF condition(cc) is true THEN dest <- sorc; Flags Affected: None CPU mode: RM,PM,VM,SMM +++++++++++++++++++++++ Physical Form & COPs: CMOVO reg,reg/mem 0FH 40H Postbyte CMOVNO reg,reg/mem 0FH 41H Postbyte CMOVC reg,reg/mem 0FH 42H Postbyte CMOVNC reg,reg/mem 0FH 43H Postbyte CMOVZ reg,reg/mem 0FH 44H Postbyte CMOVNZ reg,reg/mem 0FH 45H Postbyte CMOVNA reg,reg/mem 0FH 46H Postbyte CMOVA reg,reg/mem 0FH 47H Postbyte CMOVS reg,reg/mem 0FH 48H Postbyte CMOVNS reg,reg/mem 0FH 49H Postbyte CMOVP reg,reg/mem 0FH 4AH Postbyte CMOVNP reg,reg/mem 0FH 4BH Postbyte CMOVL reg,reg/mem 0FH 4CH Postbyte CMOVNL reg,reg/mem 0FH 4DH Postbyte CMOVNG reg,reg/mem 0FH 4EH Postbyte CMOVG reg,reg/mem 0FH 4FH Postbyte Clocks: ~1 (~pairing with other instructions) --------------------------------------------------- OPCODE CMP4S - Compare for packed BCD strings CPU: NEC/Sony all V-series Type of Instruction: User Instruction: CMP4S Description: SetFlaGS( BCD STRING (ADDRESS=ES:DI,LENGTH=CL) - BCD STRING (ADDRESS=DS:SI,LENGTH=CL) ); Note: si,di, other registers not changed Flags Affected: OF,CF,ZF ;; ZF set if RESULT of subtraction is zero. ;; CF,OF set as result of operation with most ;; signification BCDs. CPU mode: RM +++++++++++++++++++++++ Physical Form: CMP4S COP (Code of Operation) : 0FH 26H Clocks: CMP4S NEC V20: ~7+19*CL ----------------------------------------------------------------- CMPPS - Packed Single FP-Compare CPU: Pentium III+ (KNI/MMX2) Type of instruction: User Instruction: CMPPS dest,src,predicate Description: operation predicate EQ equal (dest == src) 0 LT less-than (dest < src) 1 LE less-equal (dest <= src) 2 UNORD unordered (dest ? src) 3 NEQ not-equal (dest <> src) 4 NLT not-less-that (dest => src) 5 NLE not-less-equal (dest > src) 6 ORD ordered !(dest ? src) 7 par for i = 0 to 3 do cmp = dest[] operation(predicate) src[]; if cmp = true then dest[] = 0xffffffff; else dest[] = 0x00000000; endif endfor endpar <0> = 31..0 <2> = 95..64 <1> = 63..32 <3> = 127..96 Note: Compilers may implement additional instructions: CMPEQPS xmm1,xmm2 <=> CMPPS xmm1,xmm2,0 CMPLTPS xmm1,xmm2 <=> CMPPS xmm1,xmm2,1 CMPLEPS xmm1,xmm2 <=> CMPPS xmm1,xmm2,2 CMPUNORDPS xmm1,xmm2 <=> CMPPS xmm1,xmm2,3 CMPNEQPS xmm1,xmm2 <=> CMPPS xmm1,xmm2,4 CMPNLTPS xmm1,xmm2 <=> CMPPS xmm1,xmm2,5 CMPNLEPS xmm1,xmm2 <=> CMPPS xmm1,xmm2,6 CMPORDPS xmm1,xmm2 <=> CMPPS xmm1,xmm2,7 Physical Form and Timing: CMPPS xmm1,xmm2/m128,imm8 ---- 0F C2 /r imm8 ---- 1-2 ----------------------------------------------------------------- CMPSS - Scalar Single FP-Compare CPU: Pentium III+ (KNI/MMX2) Type of instruction: User Instruction: CMPSS dest,src,predicate Description: operation predicate EQ equal (dest == src) 0 LT less-than (dest < src) 1 LE less-equal (dest <= src) 2 UNORD unordered (dest ? src) 3 NEQ not-equal (dest <> src) 4 NLT not-less-that (dest => src) 5 NLE not-less-equal (dest > src) 6 ORD ordered !(dest ? src) 7 cmp = dest[<0>] operation(predicate) src[<0>]; if cmp = true then dest[<0>] = 0xffffffff; else dest[<0>] = 0x00000000; endif <0> = 31..0 <2> = 95..64 <1> = 63..32 <3> = 127..96 Note: Compilers may implement additional instructions: CMPEQSS xmm1,xmm2 <=> CMPSS xmm1,xmm2,0 CMPLTSS xmm1,xmm2 <=> CMPSS xmm1,xmm2,1 CMPLESS xmm1,xmm2 <=> CMPSS xmm1,xmm2,2 CMPUNORDSS xmm1,xmm2 <=> CMPSS xmm1,xmm2,3 CMPNEQSS xmm1,xmm2 <=> CMPSS xmm1,xmm2,4 CMPNLTSS xmm1,xmm2 <=> CMPSS xmm1,xmm2,5 CMPNLESS xmm1,xmm2 <=> CMPSS xmm1,xmm2,6 CMPORDSS xmm1,xmm2 <=> CMPSS xmm1,xmm2,7 Physical Form and Timing: CMPSS xmm1,xmm2/m128,imm8 ---- F3 0F C2 /r imm8 ---- 1-2 --------------------------------------------------- OPCODE CMPXCHG8B - Compare and exchange 8 bytes CPU: Pentium (tm), Pentium Pro(tm), AMD Am5k86 Type of Instruction: Operation Instruction: CMPXCHG8B dest Note: dest is memory operand: QWORD PTR [memory] Description: IF ( QWORD(EDX:EAX) = dest) THEN { ZF <- 1; dest <- QWORD(ECX:EBX); } ELSE { ZF <- 0; EDX:EAX <- dest } END Flags Affected: ZF CPU mode: RM,PM,VM,SMM Physical Form: CMPXCHG8B mem64 COP (Code of Operation) : 0FH C7H Postbyte Clocks: Pentium : 10 Note: Postbyte MMRRRMMM: MM<>11 if (==) then INT 6 --------------------------------------------------- OPCODE CMPXCHG - Compare and exchange CPU: i486+ Type of Instruction: User Instruction: CMPXCHG dest,sorc Description: Acc = if OperationSize(8) -> AL OperationSize(16) -> AX OperationSize(32) -> EAX IF ( Acc = dest) THEN { ZF <- 1; dest <- sorc; } ELSE { ZF <- 0; Acc <- dest; } END Note: This instruction used to support semaphores Flags Affected: ZF ( see description) OF,SF,AF,PF,CF ( like CMP instruction ) ( see description) CPU mode: RM,PM,VM,SMM +++++++++++++++++++++++ Physical Form: CMPXCHG r/m8,r8 COP (Code of Operation) : 0FH A6H Postbyte ; i486 (A-B0 step) : 0FH B0H Postbyte ; i486 (B1+ step clones ; and upgrades) Clocks: Intel i486 : 6/7 if compare OK : 6/10 if compare FAIL Cyrix Cx486SLC : 5/7 Pentium (tm) : 6 Penalty if cache miss : Intel i486 : 2 Cyrix Cx486SLC : 1 +++++++++++++++++++++ Physical Form: CMPXCHG r/m16,r16 CMPXCHG r/m32,r32 COP (Code of Operation) : 0FH A7H Postbyte ; i486 (A-B0 step) : 0FH B1H Postbyte ; i486 (B1+ step clones ; and upgrades) Clocks: Intel i486 : 6/7 if compare OK : 6/10 if compare FAIL Cyrix Cx486SLC : 5/7 Pentium (tm) : 6 Penalty if cache miss : Intel i486 : 2 Cyrix Cx486SLC : 1 ----------------------------------------------------------------- COMISS - Scalar Ordered Single-FP Compare and Set EFLAGS CPU: Pentium III+ (KNI/MMX2) Type of instruction: User Instruction: COMISS dest,src Description: OF <- 0; SF <- 0; AF <- 0; if (dest[<0>] UNORD src[<0>]) then ZF <- 1; PF <- 1; CF <- 1; elif (dest[<0>] > src[<0>]) then ZF <- 0; PF <- 0; CF <- 0; elif (dest[<0>] < src[<0>]) then ZF <- 0; PF <- 0; CF <- 1; else ZF <- 1; PF <- 0; CF <- 0; endif <0> is 31..0 Physical Form and Timing: COMISS xmm1,xmm2/m32 ---- 0F 2F /r ---- ? --------------------------------------------------- OPCODE CPUID - CPU Identification CPU: Intel 486DX/SX/DX2 SL Enhanced and all later Intel processors include ( IntelDX4, IntelSX2, Pentium etc.), UMC microprocessors: U5S,U5SD,U5S-VL. Cyrix M1, AMD K5, Intel P6, and AMD Ehnanced Am486 CPU, such as A80486DX4-100SV8B. Note: i.e. 1993+ years processors produced by Intel Note: To know if your CPU support CPUID instruction try to set ID flag ( bit 21 of EFLAGS ) to 1, and if it sets this mean that CPUID support.(Soft). Or If Your CPU is Intel Look for '&E' signature on Top side of Chip.(Hard) Type of Instruction: Operation Instruction: CPUID Description: IF (EAX=0) THEN // All { EAX <- Maximum value of EAX to CALL CPUID instruction 1 for all processors (date 1 September 1994) may be >1 in future microprocessors ;; EBX,EDX and ECX contain a OEM name string ;; for Intel this string is 'GenuineIntel' EBX <- 756E6547H i.e. 'Genu' EDX <- 49656E69H i.e. 'ineI' ECX <- 6C65746EH i.e. 'ntel' ;; for UMC this string is 'UMC UMC UMC ' EBX <- 20434D55H i.e. 'UMC ' EDX <- 20434D55H i.e. 'UMC ' ECX <- 20434D55H i.e. 'UMC ' ;; for Cyrix this string is 'CyrixInstead' (Cx6x86,Cx5x86 steps B+) ;; for AMD this string is 'AuthenticAMD' (K6,K5,486 Enhanced CPUs) ;; for last NexGen is 'NexGenDriven' (Nx5x86 latest models) ;; for Centaur Technology is 'CentaurHauls' (IDT) ;; for Rise Technology is 'RiseRiseRise' } ELSEIF (EAX=1) THEN // All { EAX[3:0] <- Stepping ID EAX[7:4] <- Model EAX[11:8] <- Family ; 3 - 386 family ; 4 - i486 family ; 5 - Pentium family ; 6 - Pentium Pro family EAX[15:12] <- Reserved ; 0 - Original OEM processor ; 1 - OverDrive ; 2 - Dual Processor Note: Pentium P54C have pin CPUTYPE which define is this CPU First or Second e.t.c in System. So, if this chip set in "First" socket it return for example 0425h, but THIS chip return 2425h if we insert it in "Second" socket. Note: Refer to Appendix B for more information. EAX[31:16] <- Reserved and set to 0s now Note: This value in EAX[31:0] is upper 32-bit of 96-bit processor serial number. EDX <- Compability flags ;; below all info if bit flag =1 EDX[0] <- FPU: FPU on Chip EDX[1] <- VME: Virtual Mode Extention present EDX[2] <- DE: Debbuging Extentions EDX[3] <- PSE: CPU support 4MB size pages EDX[4] <- TSC: TSC present (See RDTSC command) EDX[5] <- MSR: CPU have Pentium Compatible MSRs EDX[6] <- PAE: Physical Address Extension (Intel) EDX[6] <- PTE: Support PTE (Cyrix) When set in PTE TLB will not be flushed when CR3 is written. EDX[7] <- MCE: Machine Check exception EDX[8] <- CX8: Support CMPXCHG8B instruction EDX[9] <- APIC: Local APIC on Chip (Intel) PGE: Page Global Extension (K5) EDX[10]<- reserved EDX[11]<- SEP: Fast System Call feature (Pentium Pro) EDX[12]<- MTRR: CPU support Memory Type Range Register (MTRR) EDX[13]<- PGE: Page Global Feature support EDX[14]<- MCA: Machine Check Architecture EDX[15]<- CMOV: CPU support CMOV instruction EDX[16]<- PAT: Page Attribute Table EDX[17]<- PSE36: CPU support 4MB Pages for access memory higher that 2GB. EDX[18]<- SN: CPU Support Processor Serial Number EDX[22..19] <- Reserved EDX[23] <- MMX: CPU support IA MMX EDX[24] <- FXSR: CPU Support Fast Save/Restore (IA MMX-2) EDX[25] <- SIMD: Streaming SIMD Extension (IA MMX-2) EDX[31:26] <- Reserved and set to 0s now } ELSEIF (EAX=2) { AL = 1 (Pentium Pro, Pentium II) remainder of EAX and EBX,ECX,EDX contain bytes which described cache architecture on this chip. Description of this bytes is: Value Description 00h None 01h Instruction TLB, 4K page, 4way, 64 entry 02h Instruction TLB, 4M page, 4way, 4 entry 03h Data TLB, 4K page, 4way, 64 entry 04h Data TLB, 4M page, 4way, 8 entry 06h Instruction Cache, 8K, 4 way, 32 byte per line 08h Instruction Cache, 16K, 4 way, 32 byte per line 0Ah Data cache, 8K, 2 way, 32 byte per line 0Ch Data cache, 16K, 4 way, 32 byte per line 40h No L2 cache 41h Unifed L2 cache, 32 byte per line, 4 way, 128KB 42h Unifed L2 cache, 32 byte per line, 4 way, 256KB 43h Unifed L2 cache, 32 byte per line, 4 way, 512KB 44h Unifed L2 cache, 32 byte per line, 4 way, 1MB 45h Unifed L2 cache, 32 byte per line, 4 way, 2MB (Cyrix MediaGX MMX Enhanced) 70h TLB 32-bit entry, 4 way, 4K cache 80h L1 cache 4-way associative, 16byte/line } ELSEIF (EAX = 3) // Pentium III { EDX:ECX <- Lower 64-bit of 96-bit processor serial number. } ELSEIF (EAX = 80000000h) // (K5 not SSA/5),K6, Cyrix GXm { EBX,ECX,EDX <- Undefined EAX <- Largest Extended function value recognized by CPUID. (Note: Extended CPUID functions started with 80000000h) (Example: For AMD 5k86 (K5) = 80000005h ) } ELSEIF (EAX = 80000001h) // K5,K6,Cyrix GXm,IDT Winchip 2 { EAX <- AMD Processor Signature 0000051Xh - for AMD 5k86 (K5 not SSA/5) 0000066Xh - for AMD 6k86 (K6) EBX,ECX <- Undefined EDX <- Extended Feature Flags EDX[0] <- FPU: FPU on Chip EDX[1] <- VME: Virtual Mode Extention present EDX[2] <- DE: Debbuging Extentions EDX[3] <- PSE: CPU support 4MB size pages EDX[4] <- TSC: TSC present (See RDTSC command) EDX[5] <- MSR: CPU have K5 Compatible MSRs or Cyrix Compatible MSRs EDX[6] <- PAE: Page Address Extensions EDX[7] <- MCE: Machine Check exception EDX[8] <- CX8: Support CMPXCHG8B instruction EDX[9] <- APIC: CPU have local APIC (must be enabled) EDX[10] <- Reserved EDX[11] <- SYSCALL and SYSRET Instructions (!) EDX[12]<- MTRR: Memory Type Range Registers EDX[13]<- Global Paging Extensions (PTE-PGE) EDX[14]<- MCA: Machine Check Architecture EDX[15]<- CMOV: CPU support CMOV instruction (!) EDX[16]<- FCMOV: CPU support FP. FCMOV (!) EDX[17]<- PSE: Page Size Extention EDX[21..18] <- Reserved EDX[22] <- MMXE: CPU Support Extended MMX instructions (AMD Athlon) EDX[23] <- MMX: CPU support IA MMX EDX[24] <- (Cyrix) Cyrix Extended MMX support EDX[24] <- (AMD) FXSAVE/FXRSTOR instruction support EDX[29..24] <- Reserved EDX[30] <- CPU support Extended 3DNow! Instructions EDX[31] <- AMD 3DNow! support ;Note: For AMD K5 = 000021BFh For AMD K6 = 008005BFh } ELSEIF (EAX = 80000002h,80000003h,80000004h) // AMD K5,K6, Cyrix GXm { // IDT Winchip 2 EAX, EBX, ECX ,EDX = CPU Name // Note: for AMD K5 (Don't forget x86 is BIG-Endian!!) // CPUID(EAX) EAX EBX ECX EDX // 80000002h 2D444D41 7428354B 5020296D 65636F72 // AMD- K5(r m) P roce // 80000003h 726F7373 00000000 00000000 00000000 // ssor // 80000004h 00000000 00000000 00000000 00000000 } ELSEIF (EAX = 80000005h) // AMD K5,K6,Cyrix GXm { // L1 TLB and Cache information EAX <- TLB Information (for 2M/4M pages): see format of EBX. EBX <- TLB Information (for 4K pages): EBX[31..24] <- Data TLB: Associativity (if Full assocuiativity = FFh) see CPUID 80000006h for more datails EBX[23..16] <- Data TLB: Number of Entryes EBX[15..8] <- Instruction TLB: Associativity (if Full assocuiativity = FFh) EBX[7..0] <- Instruction TLB: Number of Entryes ECX <- L1 Data Cache Information ECX[31..24] <- Size in KB ECX[23..16] <- Associativity (if full = FFh) ECX[15..8] <- Lines per Tag ECX[7..0] <- Line size in Bytes EDX <- L1 Instruction Cache Information ECX[31..24] <- Size in KB ECX[23..16] <- Associativity (if full = FFh) ECX[15..8] <- Lines per Tag ECX[7..0] <- Line size in Bytes // Note: after execution CPUID with EAX = 80000005h // reg AMD K5 AMD K6 // EBX 04800000 02800140 // ECX 08040120 20020220 // EDX 10040120 20020220 } ELSE THEN (EAX = 80000006h) // K6-III model-9, AMD Athlon { // L2 cache and TLB information EAX = 2M/4M Pages and L2 TLB Info bits description 31..28 Associativity (L2 Data TLB) 0000 L2 off 0001 Direct Mapped 0010 2-Way 0100 4-Way 0110 8-Way 1000 16-Way 1111 Full 27..16 Number of Entries (L2 Data TLB) 15..12 Associativity (L2 Instruction or Unifed TLB) 11..0 Number of entries (L2 Instruction or Unifed TLB) EBX = 4K Pages and L2 TLB Info bits description 31..28 Associativity (L2 Data TLB) 27..16 Number of Entries (L2 Data TLB) 15..12 Associativity (L2 Instruction or Unifed TLB) 11..0 Number of entries (L2 Instruction or Unifed TLB) ECX = L2 Unifed Cache Info (K6-III: only this field) bits description 31..16 Size (KB) 15..12 Associativity 11..8 Lines per tag 7..0 Line size (bytes) EDX = reserved } ELSE THEN { EAX,EBX,ECX,EDX <- Undefined } END. ------------------------------------------------------ Notes: In Tables Below, you may see that Your CPU return other features values, so in this tables, values writed on maximal. So possibly some features exists on Your CPU, but not activated in time You test, so CPUID return less functions that processor really can support ------------------------------------------------------ Table of STANDART Features (CPUID/EAX=1) by Different Vendors Media (Cyrix) 6x86 6x86L GX 6x86MX MII GXm EDX[0] <- FPU: + + + + + + EDX[1] <- VME: - - - - - - EDX[2] <- DE: - + - + + - EDX[3] <- PSE: - - - - - - EDX[4] <- TSC: - - - + + + EDX[5] <- MSR: - - - + + + EDX[6] <- PAE: - - - - - EDX[6] <- PTE: ? EDX[7] <- MCE: - - - - - - EDX[8] <- CX8: - + - + + + EDX[9] <- APIC: - - - - - EDX[10]<- res - - - - - - EDX[11]<- SEP: - - - - - - EDX[12]<- MTRR: - - - - - - EDX[13]<- PGE: - - - + + - EDX[14]<- MCA: - - - - - - EDX[15]<- CMOV: - - - + + + EDX[16]<- PAT: - - - - - - EDX[17]<- PSE36:- - - - - - EDX[18]<- SN: - - - - - - EDX[23]<- MMX: - - - + + + EDX[24]<- FXSR: - - - - - - EDX[25]<- SIMD: - - - - - - IDT IDT AMD AMD AMD AMD AMD (IDT/AMD) C6 C2 K5 K6 K6-2 K6-III Athlon EDX[0] <- FPU: + + + + + + + EDX[1] <- VME: - - + + + + + EDX[2] <- DE: + + + + + + + EDX[3] <- PSE: - - + + + + + EDX[4] <- TSC: + + + + + + + EDX[5] <- MSR: + + + + + + + EDX[6] <- PAE: - - - - - - + EDX[7] <- MCE: + + + + + + + EDX[8] <- CX8: + + + + + + + EDX[9] <- APIC: - - - - - x EDX[9] <- GPE + EDX[10]<- res - - - - - - - EDX[11]<- SEP: - - - - - - + EDX[12]<- MTRR: - - - - - - + EDX[13]<- PGE: - - - - - - + EDX[14]<- MCA: - - - - - - + EDX[15]<- CMOV: - - - - - - + EDX[16]<- PAT: - - - - - - + EDX[17]<- PSE36:- - - - - - - EDX[18]<- SN: - - - - - - - EDX[23]<- MMX: + + - + + + + EDX[24]<- FXSR: - - - - - - - EDX[25]<- SIMD: - - - - - - - Pentium Pentium Pentium Pentium (Intel) Pentium w/MMX Pro II III Celeron EDX[0] <- FPU: + + + + + + EDX[1] <- VME: + + + + + + EDX[2] <- DE: + + + + + + EDX[3] <- PSE: + + + + + + ------------------------------------------------------- EDX[4] <- TSC: + + + + + + EDX[5] <- MSR: + + + + + + EDX[6] <- PAE: - - + + + + EDX[7] <- MCE: + + + + + + ------------------------------------------------------- EDX[8] <- CX8: + + + + + + EDX[9] <- APIC: (1) (1) (1) (1) (1) (1) EDX[10]<- res - - - - ? - EDX[11]<- SEP: - - + + + + ------------------------------------------------------- EDX[12]<- MTRR: - - + + + + EDX[13]<- PGE: - - + + + + EDX[14]<- MCA: - - + + + + EDX[15]<- CMOV: - - + + + + ------------------------------------------------------- EDX[16]<- PAT: - - - (2) + + EDX[17]<- PSE36:- - - (2) + + EDX[18]<- SN: - - - - + - EDX[23]<- MMX: - + - + + + EDX[24]<- FXSR: - - - (2) + + EDX[25]<- SIMD: - - - - + - (1) = Intel produce chips with APIC and w/o APIC. (2) = It start to support since "Deschutes" core SL_enh SL_enh WB_Enh Intel Pentium UMC AMD i486SX DX/DX2 i486DX2 DX4 OVDR U5S 5x86 EDX[0] <- FPU: - + + + + - + EDX[1] <- VME: + + + + + - - EDX[2] <- DE: - - - - + - - EDX[3] <- PSE: - - + + + - - ------------------------------------------------------- EDX[4] <- TSC: - - - - + - - EDX[5] <- MSR: - - - - + - - EDX[6] <- PAE: - - - - - - - EDX[7] <- MCE: - - - - - - - ------------------------------------------------------- EDX[8] <- CX8: - - - - + - - EDX[9] <- APIC: - - - - - - - no need to look higher flags, theys is 0s. ------------------------------------------------------ Table of EXTENDED Features (CPUID/EAX=80000001) by Different Vendors Cyrix IDT IDT AMD AMD AMD AMD GXm C6 C2 K6 K6-2 K6-III Athlon EDX[0] <- FPU: + + + + + + + EDX[1] <- VME: - - - + + + + EDX[2] <- DE: - + + + + + + EDX[3] <- PSE: - - - + + + + EDX[4] <- TSC: + + + + + + + EDX[5] <- MSR: + + + + + + + EDX[6] <- PAE: - - - - - - + EDX[7] <- MCE: - + + + + + + EDX[8] <- CX8: + + + + + + + EDX[9] <- APIC: - - - - - - * EDX[10]<- res - - - + - - - EDX[11]<- SCL - - - - + + + EDX[12]<- MTRR - - - - - - + EDX[13]<- GPE - - - - + + + EDX[14]<- MCE - - - - - - + EDX[15]<- CMOV + - - - - - + EDX[16]<- PAT ? - - - - - + EDX[17]<- PSE36 - - - - - - - EDX[22]<- AMMX - - - - - - + EDX[23]<- MMX + + + + + + + EDX[24]<- EMMX + - - - - - - EDX[30]<- E3D! - - - - - - + EDX[31]<- 3D! - - + - + + + Refer to: Appendix B for more informations about CPU codes. Note: On IDT C6 CPU we may set any Identification string and family/model/ stepping info. (See MSRs 108h,109h for More Details). Here is 3 examples of Information we can may get from CPUID instruction: 1) UMC U5S Note: All UMC Chips: U5S,U5SD, 3V chips never have FPU on-chip, and never support VME Maximum Available of CPUID info entrys:1 Vendor string is : "UMC UMC UMC " Model Info : Stepping ID is : 3 Model : 2 Family : 4 M field : 0 Compability Flags: FPU on Chip :- Virtual Mode Extensions present :- CPU support I/O breakpoints :- CPU support 4MB pages :- Time Stamp Counter Presents :- CPU have Pentium compatible MSRs :- Machine Check Exception Presents :- CMPXCHG8B instruction support :- APIC on Chip :- 2) Intel 486 Note: All SL Enhanced 486: { i486SX,i486DX,i486DX2 marked '&E' on chip surface }, IntelSX2,IntelDX4 support VME !!!! But: Sxs never have FPU on chip. Maximum Available of CPUID info entrys:1 Vendor string is : "GenuineIntel" Model Info : Stepping ID is : 0 Model : 8 Family : 4 M field : 0 Compability Flags: FPU on Chip :+ Virtual Mode Extensions present :+ CPU support I/O breakpoints :- CPU support 4MB pages :- Time Stamp Counter Presents :- CPU have Pentium compatible MSRs :- Machine Check Exception Presents :- CMPXCHG8B instruction support :- APIC on Chip :- 3) Pentium Note: P54C may say that build-in APIC not present if it not supported by external hardware !!!!! (This data from P54C in single processor configuration) Maximum Available of CPUID info entrys:1 Vendor string is : "GenuineIntel" Model Info : Stepping ID is : 1 Model : 2 Family : 5 M field : 0 Compability Flags: FPU on Chip :+ Virtual Mode Extensions present :+ CPU support I/O breakpoints :+ CPU support 4MB pages :+ Time Stamp Counter Presents :+ CPU have Pentium compatible MSRs :+ Machine Check Exception Presents :+ CMPXCHG8B instruction support :+ APIC on Chip :- 4) Pentium OverDrive Note: P24T never have Machine Check Exception Maximum Available of CPUID info entrys:1 Vendor string is : "GenuineIntel" Model Info : Stepping ID is : 1 Model : 3 Family : 5 M field : 1 Compability Flags: FPU on Chip :+ Virtual Mode Extensions present :+ CPU support I/O breakpoints :+ CPU support 4MB pages :+ Time Stamp Counter Presents :+ CPU have Pentium compatible MSRs :+ Machine Check Exception Presents :- CMPXCHG8B instruction support :+ APIC on Chip :- 5) AMD Am5x86 (also AMD Enhanced 486). Maximum Available of CPUID info entrys:1 Vendor string is : "AuthenticAMD" Model Info : Stepping ID is : 4 Model : 15 Family : 4 M field : 0 Compability Flags: FPU on Chip :+ Virtual Mode Extensions present :- CPU support I/O breakpoints :- CPU support 4MB pages :- Time Stamp Counter Presents :- CPU have Pentium compatible MSRs :- P6 Flag: n/a :- Machine Check Exception Presents :- CMPXCHG8B instruction support :- 6) Pentium Pro (P6) Maximum Available of CPUID info entrys:2 <<-------------- !!!! Vendor string is : "GenuineIntel" Model Info : Stepping ID is : 1 Model : 1 Family : 6 M field : 0 Compability Flags: FPU on Chip :+ Virtual Mode Extensions present :+ CPU support I/O breakpoints :+ CPU support 4MB pages :+ Time Stamp Counter Presents :+ CPU have Pentium compatible MSRs :+ P6 Flag: n/a :+ Machine Check Exception Presents :+ CMPXCHG8B instruction support :+ APIC on Chip :+ Reserved :- ; bit 10 Fast System Call feature :+ Memory Type Range Regs. support :+ Page Global Feature support :+ Machine Check Architecture :+ CMOVxx instructions support :+ IA MMX support :+ 7) Maximum Available of CPUID info entrys:1 Vendor string is : "CyrixInstead" Compability Flags: FPU on Chip :+ Virtual Mode Extensions present :- CPU support I/O breakpoints :+ CPU support 4MB pages :- Time Stamp Counter Presents :+ CPU have Pentium compatible MSRs :+ P6 Flag: n/a :+ Machine Check Exception Presents :- CMPXCHG8B instruction support :+ APIC on Chip :- Reserved :- Reserved :- Memory Type Range Regs. support :- Page Global Feature support :+ Machine Check Architecture :- CMOVxx instructions support :+ IA MMX support :+ Note: Some Last NexGen Nx586 support CPUID instruction, but never support ID flag in EFALGS, so check it with #UD hook. Note: On Cyrix CPUs need to Enable CPUID instruction, setting CPUIDEN bit in CCR4. Note: Cyrix Cx6x86 return on CPUID(1) in EAX next data: YYYYXXMMh - where YYYY - normally 0s. XX - value of control register 0FCh (usually 05h, may be changed to any other value by user). MM - Model Unical Revision (according to DIR0) Note: Cyrix 486s never support CPUID. Flags Affected: None CPU mode: RM,PM,VM,SMM Physical Form: CPUID COP (Code of Operation): 0FH A2H Clocks: 486s & Pentium (EAX=1) : 14 486s & Pentium (EAX=0 or EAX>1) : 9 ----------------------------------------------------------------- CVTPI2PS - Packed Signed INT32 to Packed Single-FP Conversion CPU: Pentium III+ (KNI/MMX2) Type of instruction: User Instruction: CVTPI2PS dest,src Description: dest[<0>] <- (float) src[<0>]; dest[<1>] <- (float) src[<1>]; <0> is 31..0 <1> is 63..32 Physical Form and Timing: CVTPI2PS xmm,mm/m64 ---- 0F 2A /r ---- ?? ----------------------------------------------------------------- CVTPS2PI - Packed Single-FP to Packed INT32 Conversion CPU: Pentium III+ (KNI/MMX2) Type of instruction: User Instruction: CVTPS2PI dest,src Description: dest[<0>] <- (int) src[<0>]; dest[<1>] <- (int) src[<1>]; src is in Single F.P. format <0> is 31..0 <1> is 63..32 Physical Form and Timing: CVTPS2PI mm,xmm/m64 ---- 0F 2D /r ---- ?? ----------------------------------------------------------------- CVTSI2SS - Scalar Signed INT32 to Single-FP Conversion CPU: Pentium III+ (KNI/MMX2) Type of instruction: User Instruction: CVTSI2SS dest,src Description: dest[<0>] <- (float) src[<0>]; <0> is 31..0 Physical Form and Timing: CVTSI2SS xmm,r/m32 ---- F3 0F 2A /r ---- ?? ----------------------------------------------------------------- CVTSS2SI - Scalae Single-FP to Signed INT32 Conversion CPU: Pentium III+ (KNI/MMX2) Type of instruction: User Instruction: CVTSS2SI dest,src Description: dest[<0>] <- (int) src[<0>]; src is in Single F.P. format <0> is 31..0 Physical Form and Timing: CVTSS2SI r32,xmm/m32 ---- F3 0F 2D /r ---- ?? ----------------------------------------------------------------- CVTTPS2PI - Packed Single-FP to Packed INT32 Conversion (Truncate) CPU: Pentium III+ (KNI/MMX2) Type of instruction: User Instruction: CVTTPS2PI dest,src Description: dest[<0>] <- (int) src[<0>]; dest[<1>] <- (int) src[<1>]; <0> is 31..0 <1> is 63..32 Physical Form and Timing: CVTTPS2PI mm,xmm/m64 ---- 0F 2C /r ---- ?? ----------------------------------------------------------------- CVTTSS2SI - Scalar Single-FP to Signed INT32 Conversion (Truncate) CPU: Pentium III+ (KNI/MMX2) Type of instruction: User Instruction: CVTTSS2SI dest,src Description: dest[<0>] <- (int) src[<0>] if conversion is unexact returning truncate value, if result > maximal 32-bit value, result will be 0x80000000 Physical Form and Timing: CVTTSS2SI r32,xmm/m32 ---- F3 0F 2C /r ---- ?? ----------------------------------------------------------------- DIVPS - Packed Single-FP Divide CPU: Pentium III+ (KNI/MMX2) Type of instruction: User Instruction: DIVPS dest,src Description: dest[<0>] = dest[<0>] / src[<0>]; dest[<1>] = dest[<1>] / src[<1>]; dest[<2>] = dest[<2>] / src[<2>]; dest[<3>] = dest[<3>] / src[<3>]; Physical Form and Timing: DIVPS xmm1,xmm2/m128 ---- 0F 5E /r ---- 24-106 ----------------------------------------------------------------- DIVSS - Scalar Single-FP. Divide CPU: Pentium III+ (KNI/MMX2) Type of instruction: User Instruction: DIVSS dest,src Description: dest[<0>] = dest[<0>] / src[<0>]; Physical Form and Timing: DIVSS xmm1,xmm2/r32 ---- F3 0F 5E /r ---- 7-?? --------------------------------------------------- OPCODE EMMS - Empty MMX State CPU: all which supported IA MMX: Pentium (P55C only), Pentium (tm) Pro (P6) future models Type of Instruction: User Instruction: EMMS Description: FloatPointTagWord <- FFFFh Note: The EMMS instruction sets the values of the floating-point (FP) tag word to empty (all ones). EMMS marks the registers as available, so they can subsequently be used by floating-point instructions. If a floating-point instruction loads into one of the registers before it has been reset by the EMMS instruction, a floating-point stack overflow can occur, which results in a FP exception or incorrect result. All other MMX instructions validate the entire FP tag word (all zeros). This instruction must be used to dear the MMX state at the end of all MMX routines, and before calling other routines that may execute floating-point instructions. Flags affected: None Exceptions: RM PM VM SMM Description #UD #UD #UD #UD If CR0.EM = 1 #NM #NM #NM #NM If CR0.TS = 1 #MF #MF #MF #MF If pending FPU Exception ++++++++++++++++++++++++++++++++++++++ COP & Times: EMMS 0FH 77H P55C: n/a future P6: n/a --------------------------------------------------- OPCODE ESC - Escape Extrnal Cooprocessors CPU: 8086...80386, any Hybrid 486. Type of Instruction: User Instruction: ESC Number,R/M Description: This Instruction uses for Link with External Coprocessors Such as NPX. External Coprocessors look at command sequence at get ESC. CPU give Memory Operand sending to A-bus EA doing pseudo-read operation. { If 2nd Operand is Register then Do Nothing, If 2nd Operand is Memory then set EA (Effective Address) in Address Bus } First operand is Part of Command that Ext. coprocessors get. Flags Affected: None Example: ESC 0Fh,DX means FSQRT Note: ESC mnemonic was used for 8086 CPU, later all were used alternative mnemonic for cooprocessor instructions, such as FSQRT. CPU mode: RM,PM,VM,SMM +++++++++++++++++++++++ Physical Form: COP (Code of Operation) : <1101 1xxx> Postbyte Clocks: ESC n,Reg ESC n,Mem8/Mem16 8088: 2 8/12+EA 286: 9-20 9-20 386: N/A N/A 486: N/A N/A --------------------------------------------------- OPCODE EXT - Extract Bit Field CPU: NEC/Sony all V-series Type of Instruction: User Instruction: EXT start,len Description: AX <- BitField [ BASE = DS:SI START BIT OFFSET = start LENGTH = len ]; Note: si and start automatically UPDATE Flags Affected: None CPU mode: RM +++++++++++++++++++++++ Physical Form : EXT reg8,reg8 COP (Code of Operation) : 0FH 33H PostByte Clocks: EXT reg8,reg8 NEC V20: 26-55 --------------------------------------------------- OPCODE F4X4 - FPU: Multiplicate vector on Matrix 4x4 FPU: IIT FPUs. Type of Instruction: FPU instruction Instruction: F4X4 Description: ; This Instruction Multiplicate vector on ; Matrix 4X4 _ _ _ _ _ _ | | | | | | | Xn | | A00 A01 A02 A03 | | X0 | | Yn | = | A10 A11 A12 A13 | X | Y0 | | Zn | | A20 A21 A22 A23 | | Z0 | | Wn | | A30 A31 A31 A33 | | W0 | |_ _| |_ _| |_ _| ; Data fetches/stores from/to FPU registers: # of F E T C H E S STORE Register Bank0 Bank1 Bank2 Bank0 ST X0 A33 A31 Xn ST(1) Y0 A23 A21 Yn ST(2) Z0 A13 A11 Zn ST(3) W0 A03 A01 Wn ST(4) A32 A30 ST(5) A22 A20 ST(6) A12 A10 ST(7) A02 A00 Note: See FSBP0,FSBP1,FSBP2 for more information FPU Flags Affected: S FPU mode: Any Physical Form: F4X4 COP (Code of Operation): DBH F1H Clocks: IIT 2c87 : 242 IIT 3c87 : 242 IIT 3c87SX : 242 --------------------------------------------------- OPCODE FCMOVcc - Floating Point Conditional Move CPU: P6 Type of Instruction: User Instruction: FCMOVcc dest,sorc Description: IF condition(cc) is true THEN dest <- sorc; Flags Affected: Int: None Fp : None Note: Testing Integer flags: cc Meaning Test Flags Description B Below CF=1 < NB Not Below CF=0 >= E Equal ZF=1 = NE Not Equal ZF=0 != BE Below Equal (CF=1 .OR. ZF=1) <= NBE Not BelowEqual (CF=0 .AND. ZF=0) > U Unordered PF=1 NU Not Unordered PF!=1 CPU mode: RM,PM,VM,SMM +++++++++++++++++++++++ Physical Form & COPs: FCMOVB ST,STi DA C0+i FCMOVE ST,STi DA C8+i FCMOVBE ST,STi DA D0+i FCMOVU ST,STi DA D8+i FCMOVNB ST,STi DB C0+i FCMOVNE ST,STi DB C8+i FCMOVNBE ST,STi DB D0+i FCMOVNU ST,STi DB D8+i Clocks: N/A --------------------------------------------------- OPCODE FCOMI - Floating Point Compare setting Integer Flags CPU: P6 Type of Instruction: User Instruction: FuCOMIp ST0,STi Description: CASE ( result (compare(ST0,STi) ) OF { ; ZF PF CF Not Comparable: 1 1 1 ST0 > STi : 0 0 0 ST0 < STi : 0 0 1 ST0 = STi : 1 0 0 } CASE ( FP_stack_status ) OF { ; SF Overflow : 1 Underflow : 0 Otherwize : 0 } CASE ( instruction ) OF { FCOMI,FUCOMI : No FP stack adjustment; FCOMIP,FUCOMIP : POP ST; } Flags Affected: Int: CF,ZF,PF,SF Fp : None Note: In any case Sign of zero Ignored , so +0.0 = -0.0 CPU mode: RM,PM,VM,SMM +++++++++++++++++++++++ Physical Form & COPs: FCOMI ST0,STi DB F0+i FCOMIP ST0,STi DF F0+i FUCOMI ST0,STi DB E8+i FUCOMIP ST0,STi DF E8+i Clocks: N/A ----------------------------------------------- OPCODE FEMMS - Faster Enter/Exit of MMX of F.P. state CPU: AMD-3D Type of Instruction: User Instruction: FEMMS (no operands) Description: Clear MMX state after MMX instructions. (FPU.TAG <- FFFFh). Faster version of EMMS. Flags Affected: None ++++++++++++++++++++++++++++++++++ COP & Times: FEMMS 0FH 0EH --------------------------------------------------- OPCODE FINT - Finished Interrupt CPU: NEC V25,V35,V25 Plus,V35 Plus,V25 Software Guard Type of Instruction: System Instruction: FINT Description: Inticate to Internal Interrupt controller that interrupt service Routine is completed. (EOI) Flags Affected: None CPU mode: RM +++++++++++++++++++++++ Physical Form: FINT COP (Code of Operation) : 0Fh 92h Clocks: 2 --------------------------------------------------- OPCODE FNDISI - Disable NPX Interrupt FPU: i8087 only Type of Instruction: FPU instruction Instruction: FNDISI Description: CW.IEM <- 1; // Enable NPX interrupt Note: IEM is 7 of FPU.CW FPU Flags Affected: None CPU mode: 8087 support just real mode Physical Form: FNDISI COP (Code of Operation): DBH E1H Clocks: i8087 5 --------------------------------------------------- OPCODE FNENI - Enable NPX Interrupt FPU: i8087 only Type of Instruction: FPU instruction Instruction: FNENI Description: CW.IEM <- 0; // Enable NPX interrupt Note: IEM is 7 of FPU.CW FPU Flags Affected: None CPU mode: 8087 support just real mode Physical Form: FNENI COP (Code of Operation): DBH E0H Clocks: i8087 5 --------------------------------------------------- OPCODE FNSTDW - FPU Not wait Store Device Word register FPU: i387SL Mobile Type of Instruction: FPU instruction Instruction: FNSTDW dest Description: dest <- Device Word Format of Device word: bit(s) Description 0-7 Reserved 8 S - Status bit: if S=1 then FP device is a static design and OS or APM Bios may set CLK slow to 0 Mhz without lost any data. 9-15 Reserved Note: Device word register valid only after FNINIT FPU Flags Affected: None CPU mode: Any Physical Form: FNSTDW AX COP (Code of Operation): DFH E1H Clocks: i387SL Mobile: 13 --------------------------------------------------- OPCODE FNSTSG - FPU Not wait Store Signature Word register FPU: i387SL Mobile Type of Instruction: FPU instruction Instruction: FNSTSG dest Description: dest <- Signature Word Format of Signature word: bit(s) Description 3-0 Revision 7-4 Steppin 11-8 Family 15-12 Version Note: For i387(tm) SL Mobile Signature is: Version = 2 Family = 3 ; 387 Stepping = 1 ; Ax step Revision = 0 ; x0 step i.e i387(tm) SL is A0 step Note: This FPU is out of life Note: Signature word register valid only after FNINIT FPU Flags Affected: None CPU mode: Any Physical Form: FNSTSG AX COP (Code of Operation): DFH E2H Clocks: i387SL Mobile: 13 --------------------------------------------------- OPCODE FPO2 - Floating Point Operations 2nd Way CPU: NEC/Sony all V-series Type of Instruction: User Instruction: FPO2 fp_op,mem Description: This instruction was building for sending FP commands to NEC NPX which never be realized Flags Affected: None CPU mode: RM +++++++++++++++++++++++ Physical Form : FPO2 imm4,reg/mem COP (Code of Operation) : If imm4 in range 0-7 then 66H mmFFFMMM there FFF is imm4. If imm4 in range 7-F then 67H mmFFFMMM there FFF is imm4. Clocks: FPO2 imm4,reg/mem NEC V20: 2/11 --------------------------------------------------- OPCODE FRICHOP - FPU: Round to Integer chop method FPU: Cyrix FPUs and 486s with FPU on chip Type of Instruction: FPU instruction Instruction: FRICHOP Description: ST <- ROUND ( ST,CHOP ) Note: This instruction calculate rounding ST toward zero i.e. ignoring part righter that decimal . Examples: 1.2 -> 1.0 -1.2 -> -1.0 3.0 -> 3.0 0.0 -> 0.0 1.5 -> 1.0 -2.0 -> -2.0 FPU Flags Affected: S,P,D,I,C1 FPU mode: Any Physical Form: FRICHOP COP (Code of Operation): DDH FCH Clocks: Cx83D87 : 15 Cx83S87 : 15 CxEMC87 : 15 Cx487DLC : --------------------------------------------------- OPCODE FRINEAR - FPU: Round to Integer Nearest method FPU: Cyrix FPUs and 486s with FPU on chip Type of Instruction: FPU instruction Instruction: FRINEAR Description: ST <- ROUND ( ST,NEAREST ) Note: This instruction calculate rounding ST toward nearest Examples: 1.2 -> 1.0 -1.2 -> -1.0 3.0 -> 3.0 0.0 -> 0.0 1.5 -> 1.0 1.8 -> 2.0 -2.0 -> -2.0 FPU Flags Affected: S,P,D,I,C1 FPU mode: Any Physical Form: FRINEAR COP (Code of Operation): DFH FCH Clocks: Cx83D87 : 15 Cx83S87 : 15 CxEMC87 : 15 Cx487DLC : --------------------------------------------------- OPCODE FRINT2 - FPU: Round to Integer FPU: Cyrix FPUs and 486s with FPU on chip Type of Instruction: FPU instruction Instruction: FRINT2 Description: IF ( exact half ) THEN { ST <- SIGN(ST) * ROUND(ABS(ST)+0.5,NEAREST) } ELSE { ST <- ROUND ( ST,NEAREST ) } END Note: This instruction calculate rounding ST toward nearest, but if number is exact half then this instruction round it toward signed infinity. Sign of this infinity is same with sign of number. Examples: 1.2 -> 1.0 -1.2 -> -1.0 3.0 -> 3.0 0.0 -> 0.0 1.5 -> 2.0 1.8 -> 2.0 -2.0 -> -2.0 -1.5 -> -2.0 FPU Flags Affected: S,P,D,I,C1 FPU mode: Any Physical Form: FRINT2 COP (Code of Operation): DBH FCH Clocks: Cx83D87 : 15 Cx83S87 : 15 CxEMC87 : 15 Cx487DLC : --------------------------------------------------- OPCODE FRSTPM - FPU Reset Protected Mode FPU: i287XL i287XLT Type of Instruction: FPU instruction Instruction: FRSTPM Description: Reset Cooprocessor from Protected Mode to Real Address mode. FPU Flags Affected: None CPU mode:Any ??? Physical Form: FRSTPM COP (Code of Operation): DBH E5H Clocks: i287XL : 12 i287XLT : 12 --------------------------------------------------- OPCODE FSBP0 - FPU: Set Bank pointer to Bank # 0 FPU: IIT FPUs. Type of Instruction: FPU instruction Instruction: FSBP0 Description: ; This Instruction set current bank pointer to ; Bank # 0. ; Each bank contain eight 80bit registers ; There are 3 banks (0,1,2) in Chip ; After initialization FPU select bank # 0. FPU Flags Affected: None FPU mode: Any Physical Form: FSBP0 COP (Code of Operation): DBH E8H Clocks: IIT 2c87 : 6 IIT 3c87 : 6 IIT 3c87SX : 6 --------------------------------------------------- OPCODE FSBP1 - FPU: Set Bank pointer to Bank # 1 FPU: IIT FPUs. Type of Instruction: FPU instruction Instruction: FSBP1 Description: ; This Instruction set current bank pointer to ; Bank # 1. ; Each bank contain eight 80bit registers ; There are 3 banks (0,1,2) in Chip ; After initialization FPU select bank # 0. FPU Flags Affected: None FPU mode: Any Physical Form: FSBP1 COP (Code of Operation): DBH EBH Clocks: IIT 2c87 : 6 IIT 3c87 : 6 IIT 3c87SX : 6 --------------------------------------------------- OPCODE FSBP2 - FPU: Set Bank pointer to Bank # 2 FPU: IIT FPUs. Type of Instruction: FPU instruction Instruction: FSBP2 Description: ; This Instruction set current bank pointer to ; Bank # 2. ; Each bank contain eight 80bit registers ; There are 3 banks (0,1,2) in Chip ; After initialization FPU select bank # 0. FPU Flags Affected: None FPU mode: Any Physical Form: FSBP2 COP (Code of Operation): DBH EAH Clocks: IIT 2c87 : 6 IIT 3c87 : 6 IIT 3c87SX : 6 --------------------------------------------------- OPCODE FSETPM - FPU Set Protected Mode Adressing FPU: 80287, i287XL i287XLT Type of Instruction: FPU instruction Instruction: FRSTPM Description: Setup Coprocessor for addressing in Protected mode FPU Flags Affected: None CPU mode:Any ??? Physical Form: FSETPM COP (Code of Operation): DBH E4H Clocks: i287XL : 12 i287XLT : 12 --------------------------------------------------- OPCODE FXRSTOR - Fast Restore F.P. Context CPU: Katmai/Deschutes (IA MMX-2) Type of Instruction: User Instruction: FXRSTOR src Description: Fast Restore 94 (16-bit mode) or 108 (32-bit mode) byte of F.P. context to memory. Format of context as in standart x86 instruction: FSAVE. Note: Check CPUID, EAX=1, bit 24 for knew CPU support this feature. And then look at CR4.bit9. Note: See FXSAVE for more information Flags Affected: None CPU mode: any +++++++++++++++++++++++ Physical Form & COPs: FXRSTOR mem512byte 0F AE mm001mmm Clocks: n/a --------------------------------------------------- OPCODE FXSAVE - Fast Save F.P. Context CPU: Pentium II (Deschutes) + Type of Instruction: User Instruction: FXSAVE dest Description: Fast Save 94 (16-bit mode) or 108 (32-bit mode) byte of F.P. context to memory. Format of context as in standart x86 instruction: FSAVE. Note: Check CPUID, EAX=1, bit 24 for knew CPU support this feature. And then look at CR4.bit9. Format of F.P./MMX Save Area: Offset (hex) Size Description +00 WORD FCW (Control word) +02 WORD FSW (Status word) +04 WORD FTW (Tag word) +06 WORD FOP (lower 11-bit F.P. opcode) +08 DWORD IP (F.P. Instruction pointer) +0C WORD CS +10 DWORD DP (F.P. Data pointer) +14 WORD DS +18 DWORD MXCSR (Pentium III+) see LDMXCSR instruction for more info +20 TBYTE ST0/MM0 +30 TBYTE ST1/MM1 +40 TBYTE ST2/MM2 +50 TBYTE ST3/MM3 +60 TBYTE ST4/MM4 +70 TBYTE ST5/MM5 +80 TBYTE ST6/MM6 +90 TBYTE ST7/MM7 +A0 16BYTE XMM0 (Pentium III+) +B0 16BYTE XMM1 (Pentium III+) +C0 16BYTE XMM2 (Pentium III+) +D0 16BYTE XMM3 (Pentium III+) +E0 16BYTE XMM4 (Pentium III+) +F0 16BYTE XMM5 (Pentium III+) +100 16BYTE XMM6 (Pentium III+) +110 16BYTE XMM7 (Pentium III+) All other fields are reserved. Full length of Save/Restore area is 512 byte. (200h) Flags Affected: None CPU mode: any +++++++++++++++++++++++ Physical Form & COPs: FXSAVE mem512byte 0F AE mm000mmm Clocks: n/a --------------------------------------------------- OPCODE IBTS - Insert Bits String CPU: 80386 step A0-B0 only Type of Instruction: User Instruction: IBTS base,bitoffset,len,sorc Description: Write bit string length bits from [bits .. 0 ] (lowest bits) to bitfield, defined by and bitsoffset from this base to start of the field to write. String write from this start field bit to higher memory addresses or register bits. Flags Affected: None CPU mode: RM,PM,VM +++++++++++++++++++++++ Physical Form: IBTS r/m16,AX,CL,r16 IBTS r/m32,EAX,CL,r32 COP (Code of Operation) : 0FH A7H Postbyte Clocks: IBTS 80386: 12/19 --------------------------------------------------- OPCODE ICEBP - PWI Mode BreakPoint, ICE address space CPU: IBM 486SLC2 Type of Instruction: System Instruction: ICEBP Description: IF (condition) THEN ; see condition below { SAVE STATUS OF EXECUTION TO ICE space; ENTER SMM; } ELSE { INT 1; } END Note: This condition can be set before execution this instruction: CPL=0 MSR1000H.EPCEA=1 MSR1000H.EPWI=1 See Appendix X for more info. Flags Affected: None CPU mode: RM,PM0 Physical Form: ICEBP COP (Code of Operation): F1H Clocks: IBM 486SLC2 : 460 --------------------------------------------------- OPCODE ICEBP - In-Circuit Emulator Breakpoint CPU: some models of i486, i386, Pentium, Pentium Pro Type of Instruction: System Instruction: ICEBP Description: IF (condition) THEN ; see condition below { CHANGED TO THE ICE instruction mode; } ELSE { INT 1; } END Note: 386/486: Condition is DR7.bit12=1 (CPU must be supported ICE). Note: This instruction very usefull to debbuging as Single-Byte Interrupt but it generate never int 3, but int 1. Note: On Pentium Interrupt redirection initiately disabled on PMCR (Probe Mode Control Register), which is only accessable via debug port i.e. Need external hardware for enable normal ICEBP execution. Note: On Pentium Pro situation is the same. But in Pentium Pro Intel named this instruction INT01. Flags Affected: None CPU mode: RM,PM0 Physical Form: ICEBP COP (Code of Operation): F1H Clocks: : N/A --------------------------------------------------- OPCODE ICERET - Return from PWI mode, ICE space CPU: IBM 486SLC2 Type of Instruction: System Operation (Work only then CPL=0) Instruction: ICERET Description: Load All Registers (Include Shadow Registers) from Table Which Begin on place pointed ES:EDI, and return from PWI mode. Format of ICERET Table: Offset Len Description 0H 4 CR0 4H 4 EFLAGS 8H 4 EIP CH 4 EDI 10H 4 ESI 14H 4 EBP 18H 4 ESP 1CH 4 EBX 20H 4 EDX 24H 4 ESX 28H 4 EAX 2CH 4 DR6 30H 4 DR7 34H 4 TR (16 bit, zero filled up) 38H 4 LDT --------- 3CH 4 GS --------- 40H 4 FS --------- 44H 4 DS --------- 48H 4 SS --------- 4CH 4 CS --------- 50H 4 ES --------- 54H 4 TSS.attrib 58H 4 TSS.base 5CH 4 TSS.limit 60H 4 Reserved 64H 4 IDT.base 68H 4 IDT.limit 6CH 4 REP OUTS overrun flag 70H 4 GDT.base 74H 4 GDT.limit 78H 4 LDT.attrib 7CH 4 LDT.base 80H 4 LDT.limit 84H 4 GS.attrib 88H 4 GS.base 8CH 4 GS.limit 90H 4 FS.attrib 94H 4 FS.base 98H 4 FS.limit 9CH 4 DS.attrib A0H 4 DS.base A4H 4 DS.limit A8H 4 SS.attrib ACH 4 SS.base B0H 4 SS.limit B4H 4 CS.attrib B8H 4 CS.base BCH 4 CS.limit C0H 4 ES.attrib C4H 4 ES.base C8H 4 ES.limit Unknown Unusable area ;; Temporary registers: 100H 4 TST 104H 4 IDX 108H 4 TMPH 10CH 4 TMPG 110H 4 TMPF 114H 4 TMPE 118H 4 TMPD 11CH 4 TMPC 120H 4 TMPB 124H 4 TMPA 128H 4 CR2 12CH 4 CR3 130H 4 MSR1001H (31-0) 134H 4 MSR1001H (63-32) 138H 4 MSR1000H (15-0) 13CH 4 DR0 140H 4 DR1 144H 4 DR2 148H 4 DR3 14CH 4 PEIP Length of table is 150H bytes. see Appendix X for more info. Note: For descriptor format refer to LOADALL and RES3 instructions. Flags Affected: All (FLAGS Register Reload) CPU mode: SMM Physical Form: ICERET COP (Code of Operation): 0FH 07H Note: Code is same with Intel's LOADALL Clocks: IBM 486SLC2 : 440 --------------------------------------------------- OPCODE INS - Insert Bit String CPU: NEC/Sony all V-series Type of Instruction: User Instruction: INS start,len Description: BitField [ BASE = ES:DI START BIT OFFSET = start LENGTH = len ] <- AX [ bits= (len-1)..0] Note: di and start automatically UPDATE Note: Alternative Name of this instruction is NECINS Flags Affected: None CPU mode: RM +++++++++++++++++++++++ Physical Form : INS reg8,reg8 COP (Code of Operation) : 0FH 31H PostByte Clocks: INS reg8,reg8 NEC V20: 31-117 --------------------------------------------------- OPCODE INVD - Invalidate Cache Buffer CPU: I486 + Type of Instruction: System Instruction: INVD Description: FLUSH INTERNAL CACHE ( It means that all lines of internal caches sets as invalid ) SIGNAL EXTERNAL CACHE TO FLUSH Notes: This instruction not work in Real Mode and in Protected mode work only in ring 0 ; Flags Affected: None CPU mode: PM0,SMM? Physical Form: INVD COP (Code of Operation): 0FH 08H Clocks: Cyrix Cx486SLC : 4 i486 : 4 Pentium : 15 --------------------------------------------------- OPCODE INVLPG - Invalidate Page Entry In TLB CPU: I486 + Type of Instruction: System Instruction: INVLPG mem Description: IF found in data or code (if both) (or common if single) TLB entry with linear address (page part) same as memory operand then mark this entry as Invalid; Notes: This instruction not work in Real Mode and in Protected mode work only in ring 0 ; Flags Affected: None CPU mode: RM,PM,VM,SMM Physical Form: INVLPG mem COP (Code of Operation): 0FH 01H mm111mmm Clocks: Cyrix Cx486SLC : 4 i486 : 12 if hit : 11 if not hit Pentium : 25 --------------------------------------------------- OPCODE JMPE - Jump and change to 64-bit ISA. CPU: Merced Type of Instruction: User Instruction: JMPX dest_addr Description: This instruction make jump to specified address, and change execution mode from IA-32 to IA-64. (So address must be 16-byte aligned). Note: The other method to cnange execution mode to IA-64 is interrupt to 64-bit code or IRET in IA-32 routine, which will be called from IA-64. back to IA-32 mode using commands: br.ia, rti and via interrupt. Flags Affected: None CPU mode: IA-32 Physical Form: JMPX rel16/rel32 0F B8 rel16/rel32 JMPX r/m(16/32) 0F 00 /6 COP (Code of Operation): Clocks: Merced : ----------------------------------------------------------------- LDMXCSR - Load Streaming SIMD Extension Control/Status CPU: Pentium III+ (KNI/MMX2) Type of instruction: User Instruction: LDMXCSR src Description: MXCSR <- src; Format of MXCSR: Bits Description 31..16 Reserved 15 FZ (Flush to Zero) 14..13 RC (Round Control) 00 Round to nearest (even) 01 Round down (to minius infinity) 10 Round up (to positive infinity) 11 Round toward zero (Truncate) 12 PM (SIMD numeric exception masks) 11 UM 10 OM 9 ZM 8 DM 7 IM 6 Reserved 5 PE (SIMD numeric exceptions) 4 UE 3 OE 2 ZE 1 DE 0 IE Physical Form and Timing: LDMXCSR m32 ---- 0F AE /2 ---- ?? --------------------------------------------------- OPCODE LOADALL - Load All Registers CPU: Intel 386+ +all clones Type of Instruction: System (Work only then CPL=0) Instruction: LOADALL Description: Load All Registers (Include Shadow Registers) from Table Which Begin on place pointed ES:EDI Format of LOADALL Table: Offset Len Description 0H 4 CR0 4H 4 EFLAGS 8H 4 EIP CH 4 EDI 10H 4 ESI 14H 4 EBP 18H 4 ESP 1CH 4 EBX 20H 4 EDX 24H 4 ESX 28H 4 EAX 2CH 4 DR6 30H 4 DR7 34H 4 TR (16 bit, zero filled up) 38H 4 LDT --------- 3CH 4 GS --------- 40H 4 FS --------- 44H 4 DS --------- 48H 4 SS --------- 4CH 4 CS --------- 50H 4 ES --------- 54H 4 TSS.attrib 58H 4 TSS.base 5CH 4 TSS.limit 60H 4 0s 64H 4 IDT.base 68H 4 IDT.limit 6CH 4 0s 70H 4 GDT.base 74H 4 GDT.limit 78H 4 LDT.attrib 7CH 4 LDT.base 80H 4 LDT.limit 84H 4 GS.attrib 88H 4 GS.base 8CH 4 GS.limit 90H 4 FS.attrib 94H 4 FS.base 98H 4 FS.limit 9CH 4 DS.attrib A0H 4 DS.base A4H 4 DS.limit A8H 4 SS.attrib ACH 4 SS.base B0H 4 SS.limit B4H 4 CS.attrib B8H 4 CS.base BCH 4 CS.limit C0H 4 ES.attrib C4H 4 ES.base C8H 4 ES.limit CCH 4 Length of table D0H 30h Unused,not loaded 100H 4 Temporary Register IST 104H 4 Temporary Register I 108H 4 Temporary Register H 10CH 4 Temporary Register G 110H 4 Temporary Register F 114H 4 Temporary Register E 118H 4 Temporary Register D 11CH 4 Temporary Register C 120H 4 Temporary Register B 124H 4 Temporary Register A Format of Attrib field: Byte Description 0 0s 1 AR (Access Right) byte in the Descriptor format Note: P bit is a valid bit if valid bit=0 then Shadow Register is invalid and INT 0DH - General Protection Fault call DPL of SS,CS det. CPL 2-3 0s Flags Affected: All (FLAGS Register Reload) CPU mode: RM,PM0 Physical Form: LOADALL COP (Code of Operation): 0FH 07H Clocks: i386XX : n/a i486XX : n/a Note: This operation used 102 data transfer cycles on 32bit bus Typical clocks: i386SX: ~350 i386DX: ~290 i486XX: ~220 --------------------------------------------------- OPCODE LOADALL - Load All Registers From Table CPU: Intel 80286 and all its clones Type of Instruction: System (Work only then CPL=0) Instruction: LOADALL Description: Load All Registers (Include Shadow Registers) from Table Which Begin on 000800H Address, Len of this table is 66H Format of LOADALL Table: Address Len Description 800H 6 None 806H 2 MSW 808H 14 None 816H 2 TR 818H 2 FLAGS 81AH 2 IP 81CH 2 LDTR 81EH 2 DS 820H 2 SS 822H 2 CS 824H 2 ES 826H 2 DI 828H 2 SI 82AH 2 BP 82CH 2 SP 82EH 2 BX 830H 2 DX 832H 2 CX 834H 2 AX 836H 6 ES Shadow Descriptor 83CH 6 CS Shadow Descriptor 842H 6 SS Shadow Descriptor 848H 6 DS Shadow Descriptor 84EH 6 GDTR 854H 6 LDT Shadow Descriptor 85AH 6 IDTR 860H 6 TSS Shadow Descriptor Format of Shadow Descriptor: Byte Description 0-2 24bit Phisical Address 3 AR (Access Right) byte 4-5 16bit Segment Limit Format of GDTR and IDTR: Byte Description 0-2 24bit Phisical Address 3 0s 4-5 16bit Segment Limit Note: Using this instruction we may turn on "Big Real Mode" i.e. mode then PG=1,PE=0,cpl=0. This mode very usefull,But Pentium never support this instruction. Flags Affected: All (FLAGS Register Reload) CPU mode: RM,PM0 Physical Form: LOADALL COP (Code of Operation): 0FH 05H Clocks: 80286 : 195 ----------------------------------------------------------------- MASKMOVQ - Byte Mask Write CPU: Pentium III+ (KNI/MMX2), Athlon+ (AMD EMMX) Type of instruction: User Instruction: MASKMOVQ src,mask Description: #define MOVE_BYTE(check_bit,move_bits) if (mask[check_bit] == 1) mem64[EDI][move_bits] = src[move_bits]; else mem64[EDI][move_bits] = 0; endif; #enddef MOVE_BYTE(7 , 7..0); MOVE_BYTE(15, 15..8); MOVE_BYTE(23, 23..16); MOVE_BYTE(31, 31..24); MOVE_BYTE(39, 39..32); MOVE_BYTE(47, 47..40); MOVE_BYTE(55, 55..48); MOVE_BYTE(63, 63..56); Physical Form and Timing: MASKMOVQ mm1,mm2 ---- 0F F7 /r ---- ?? ----------------------------------------------------------------- MAXPS - Packed Single-FP Maximum CPU: Pentium III+ (KNI/MMX2) Type of instruction: User Instruction: MAXPS dest,src Description: par for i=0 to 3 do if dest[] is NaN then dest[] <- src[]; if src[] is NaN then dest[] <- src[]; if src[] >= dest[] then dest[] <- src[]; endfor; <0> = 31..0 <2> = 95..64 <1> = 63..32 <3> = 127..96 Physical Form and Timing: MAXPS xmm1,xmm2/m128 ---- 0F 5F /r ---- 2 ----------------------------------------------------------------- MAXSS - Scalar Single-FP Maximum CPU: Pentium III+ (KNI/MMX2) Type of instruction: User Instruction: MAXSS dest,src Description: if dest[<0>] is NaN then dest[<0>] <- src[<0>]; if src[<0>] is NaN then dest[<0>] <- src[<0>]; if src[<0>] >= dest[<0>] then dest[<0>] <- src[<0>]; Physical Form and Timing: MAXSS xmm1,xmm2/m32 ---- F3 0F 5F /r ---- 1 ----------------------------------------------------------------- MINPS - Packed Single-FP Minimum CPU: Pentium III+ (KNI/MMX2) Type of instruction: User Instruction: MINPS dest,src Description: par for i=0 to 3 do if dest[] is NaN then dest[] <- src[]; if src[] is NaN then dest[] <- src[]; if src[] < dest[] then dest[] <- src[]; endfor; <0> = 31..0 <2> = 95..64 <1> = 63..32 <3> = 127..96 Physical Form and Timing: MINPS xmm1,xmm2/m128 ---- 0F 5D /r ---- 2 ----------------------------------------------------------------- MINSS - Scalar Single-FP Manimum CPU: Pentium III+ (KNI/MMX2) Type of instruction: User Instruction: MINSS dest,src Description: if dest[<0>] is NaN then dest[<0>] <- src[<0>]; if src[<0>] is NaN then dest[<0>] <- src[<0>]; if src[<0>] < dest[<0>] then dest[<0>] <- src[<0>]; Physical Form and Timing: MINSS xmm1,xmm2/m32 ---- F3 0F 5D /r ---- 1 ----------------------------------------------------------------- MOVAPS - Move Aligned Four Packed Single-FP CPU: Pentium III+ (KNI/MMX2) Type of instruction: User Instruction: MOVAPS dest,src Description: dest <- src; Note: This instruction moved 16-byte (128-bit) total size 4x 32-bit FP. from/to memory. Address of this F.P. block must be 16-bytes aligned Physical Form and Timing: MOVAPS xmm1,xmm2/m128 ---- 0F 28 /r ---- ?? MOVAPS xmm2/m128,xmm1 ---- 0F 29 /r ---- ?? --------------------------------------------------- OPCODE MOVD - Move Dwords CPU: all which supported IA MMX: Pentium (P55C only), Pentium (tm) Pro (P6) future models Type of Instruction: User Instruction: MOVD dest,src Description: IF dest is MMi register THEN { dest[63..32] <- 0 dest[31..0] <- src } ELSE ; If dest is DWORD dest <- src [31..0] Note: This instruction moved DWORDs to/from MMX registers Flags affected: None Exceptions: RM PM VM SMM Description #GP(0) If result in Non-Writable segment #GP(0) If Illegal memory operand's EA in CS,DS,ES,FS,GS #SS(0) If illegal memory operand's EA in SS #PF(fcode) If page fault #AC #AC If unaligned memory reference then alignment check enabled and in ring 3. #UD #UD #UD #UD If CR0.EM = 1 #NM #NM #NM #NM If CR0.TS = 1 #MF #MF #MF #MF If pending FPU Exception ++++++++++++++++++++++++++++++++++++++ COP & Times: MOVD mm,r/m32 0FH 6EH PostByte MOVD r/m32,mm 0Fh 7Eh PostByte mm,r/m32 r/m32,mm P55C: n/a (~1) (~1) future P6: n/a (~1) (~1) ----------------------------------------------------------------- MOVHLPS - Move High to Low Packed Single-F.P. CPU: Pentium III+ (KNI/MMX2) Type of instruction: User Instruction: MOVHLPS dest,src Description: dest[<1>] <- src[<3>]; dest[<0>] <- src[<2>]; <0> = 31..0 <2> = 95..64 <1> = 63..32 <3> = 127..96 Physical Form and Timing: MOVHLPS xmm1,xmm2 ---- 0F 12 /r ---- 1 ----------------------------------------------------------------- MOVHPS - Move High Packed Single FP. CPU: Pentium III+ (KNI/MMX2) Type of instruction: User Instruction: MOVHPS dest,src Description: if (dest is mem64) then dest[<1>] <- src[<3>]; dest[<0>] <- src[<2>]; endif if (src is mem64) then dest[<3>] <- src[<1>]; dest[<2>] <- src[<0>]; endif <0> = 31..0 <2> = 95..64 <1> = 63..32 <3> = 127..96 Physical Form and Timing: MOVHPS xmm,m64 ---- 0F 16 /r ---- 1 MOVHPS m64,xmm ---- 0F 17 /r ---- 1 ----------------------------------------------------------------- MOVLHPS - Move Low to High Packed Single-F.P. CPU: Pentium III+ (KNI/MMX2) Type of instruction: User Instruction: MOVLHPS dest,src Description: dest[<3>] <- src[<1>]; dest[<2>] <- src[<0>]; <0> = 31..0 <2> = 95..64 <1> = 63..32 <3> = 127..96 Physical Form and Timing: MOVLHPS xmm1,xmm2 ---- 0F 16 /r ---- 1 ----------------------------------------------------------------- MOVLPS - Move Low Packed Single FP. CPU: Pentium III+ (KNI/MMX2) Type of instruction: User Instruction: MOVLPS dest,src Description: dest[<1>] <- src[<1>]; dest[<0>] <- src[<0>]; <0> = 31..0 <2> = 95..64 <1> = 63..32 <3> = 127..96 Physical Form and Timing: MOVLPS xmm,m64 ---- 0F 12 /r ---- 1 MOVLPS m64,xmm ---- 0F 13 /r ---- 1 ----------------------------------------------------------------- MOVMSKPS - Move Mask to Integer CPU: Pentium III+ (KNI/MMX2) Type of instruction: User Instruction: MOVMSKPS dest,src Description: dest[0] <- src[31]; // Single Bits, not bit groups dest[1] <- src[63]; dest[2] <- src[95]; dest[3] <- src[127]; dest[31..4] <- 0; Physical Form and Timing: MOVMSKPS r32,xmm ---- 0F 50 /m ---- ?? ----------------------------------------------------------------- MOVNTPS - Move Aligned Four Packed Single-FP Non Temporal CPU: Pentium III+ (KNI/MMX2) Type of instruction: User Instruction: MOVNTPS dest,src Description: dest <- src; // This store mimimize cache pollution // storing XMM 128-bit register Physical Form and Timing: MOVNTPS m128,xmm ---- 0F 2B /r ---- ?? ----------------------------------------------------------------- MOVNTQ - Move 64 bits non temporal CPU: Pentium III+ (KNI/MMX2), AMD Athlon (AMD EMMX) Type of instruction: User Instruction: MOVNTQ dest,src Description: dest <- src; // This store minimize cache pollution // storing MM (MMX) 64-bit register Physical Form and Timing: MOVNTQ m64,mm ---- 0F E7 /r ---- ?? --------------------------------------------------- OPCODE MOVQ - Move Qwords CPU: all which supported IA MMX: Pentium (P55C only), Pentium (tm) Pro (P6) future models Type of Instruction: User Instruction: MOVQ dest,src Description: dest <- src Note: This instruction moved QWORDs to/from MMX registers Of course, IA support Big-endian QWORDS. Flags affected: None Exceptions: RM PM VM SMM Description #GP(0) If result in Non-Writable segment #GP(0) If Illegal memory operand's EA in CS,DS,ES,FS,GS #SS(0) If illegal memory operand's EA in SS #PF(fcode) If page fault #AC #AC If unaligned memory reference then alignment check enabled and in ring 3. #UD #UD #UD #UD If CR0.EM = 1 #NM #NM #NM #NM If CR0.TS = 1 #MF #MF #MF #MF If pending FPU Exception ++++++++++++++++++++++++++++++++++++++ COP & Times: MOVQ mm,mm/m64 0FH 6FH PostByte MOVQ mm/m64,mm 0Fh 7Fh PostByte Note: In PostByte instead IU registers used MMX registers, 0Fh 6Fh C0h means MOVQ MM0,MM0 mm,r/m32 r/m32,mm P55C: n/a (~1) (~1) future P6: n/a (~1) (~1) --------------------------------------------------- OPCODE MOVSPA - Move Stack Pointer After Bank Switched CPU: NEC V25,V35,V25 Plus,V35 Plus,V25 Software Guard Type of Instruction: System Instruction: MOVSPA Description: This instruction transfer both SS and SP of the old register bank to new register bank after the bank has been switched by interrupt or BRKCS instruction. Flags Affected: None CPU mode: RM +++++++++++++++++++++++ Physical Form: MOVSPA COP (Code of Operation) : 0Fh 25h Clocks: 16 --------------------------------------------------- OPCODE MOVSPB - Move Stack Pointer Before Bamk Switching CPU: NEC V25,V35,V25 Plus,V35 Plus,V25 Software Guard Type of Instruction: System Instruction: MOVSPB Number_of_bank Description: The MOVSPB instruction transfers the current SP and SS before the bank switching to new register bank. Note: New Register Bank Number indicated by lower 3bit of Number_of_ _bank. Note: See BRKCS instruction for more info about banks. Flags Affected: None CPU mode: RM +++++++++++++++++++++++ Physical Form: MOVSPB reg16 COP (Code of Operation) : 0Fh 95h <1111 1RRR> Clocks: 11 ----------------------------------------------------------------- MOVSS - Move Scalar Single-FP CPU: Pentium III+ (KNI/MMX2) Type of instruction: User Instruction: MOVSS dest,src Description: dest[<0>] <- src[<0>]; <0> = 31..0 <2> = 95..64 <1> = 63..32 <3> = 127..96 Physical Form and Timing: MOVSS xmm1,xmm2/m32 ---- F3 0F 10 /r ---- ?? MOVSS xmm2/m32,xmm1 ---- F3 0F 11 /r ---- ?? ----------------------------------------------------------------- MOVUPS - Move Unaligned Four Packed Single-FP CPU: Pentium III+ (KNI/MMX2) Type of instruction: User Instruction: MOVUPS dest,src Description: dest <- src // Analigned move of XMM 128-bit register Physical Form and Timing: MOVUPS xmm1,xmm2/m128 ---- 0F 10 /r ---- ?? MOVUPS xmm2/m128,xmm1 ---- 0F 11 /r ---- ?? ----------------------------------------------------------------- MULPS - Packed Single-FP Multiply CPU: Pentium III+ (KNI/MMX2) Type of instruction: User Instruction: MULPS dest,src Description: dest[<0>] = dest[<0>] * src[<0>]; dest[<1>] = dest[<1>] * src[<1>]; dest[<2>] = dest[<2>] * src[<2>]; dest[<3>] = dest[<3>] * src[<3>]; Physical Form and Timing: MULPS xmm1,xmm2/m128 ---- 0F 59 /r ---- 2 ----------------------------------------------------------------- MULSS - Scalar Single-FP Multiply CPU: Pentium III+ (KNI/MMX2) Type of instruction: User Instruction: MULPS dest,src Description: dest[<0>] = dest[<0>] * src[<0>]; Physical Form and Timing: MULSS xmm1,xmm2/m32 ---- F3 0F 59 /r ---- 2 --------------------------------------------------- OPCODE NOT1 - Invert a Specified bit CPU: NEC/Sony all V-series Type of Instruction: User Instruction: NOT1 dest,bitnumb Description: (BIT bitnumb OF dest) <- NOT (BIT bitnumb OF dest); Flags Affected: None CPU mode: RM +++++++++++++++++++++++ Physical Form: NOT1 reg/mem8,CL COP (Code of Operation) : 0FH 16H Postbyte Physical Form: NOT1 reg/mem8,imm8 COP (Code of Operation) : 0FH 1EH Postbyte imm8 Physical Form: NOT1 reg/mem16,CL COP (Code of Operation) : 0FH 17H Postbyte Physical Form: NOT1 reg/mem16,imm8 COP (Code of Operation) : 0FH 1FH Postbyte imm8 Clocks: NOT1 r/m8,CL r/m8,i8 r/m16,CL r/m16,i8 NEC V20: 4/18 5/19 4/18 5/19 -------------------------------------------------- OPCODE OIO - Official Undefined Opcode CPU: Cyrix Cx6x86 (same code on AMD Am5k86) Logical Form: OIO Description: Caused #UD exception Flags Affected: No Flags Affected CPU Mode : RM,PM,VM,VME,SMM Exceptions : RM PM V86 VME SMM #UD #UD #UD #UD #UD Undefined Instruction No more Exceptions Note : This instruction caused #UD. AMD guaranteed that in future AMD's CPUs this instruction will caused #UD. Of course all previous CPUs (186+) caused #UD on this opcode. This instruction used by software writers for testing #UD exception servise routine. ++++++++++++++++++++++++++++++ Physical Form : UD COP (Code of Operation) : 0Fh FFh Clocks : UD 8088: Not supported NEC V20: Not supported 80186: ~int 80286: ~int 80386: ~int Cx486SLC: ~int i486: ~int Cx486DX: ~int Cx5x86: ~int Pentium: ~int Nx5x86: ~int Cx6x86: ~int Am5k86: ~int Pentium Pro: ~int ++++++++++++++++++++++++++++++ ----------------------------------------------------------------- ORPS - Bit-wise Logical OR For Single-FP CPU: Pentium III+ (KNI/MMX2) Type of instruction: User Instruction: ORPS dest,src Description: dest = dest OR src; // Bitwize 128-bit Physical Form and Timing: ORPS xmm1,xmm2/m128 ---- 0F 56 /r ---- 2 --------------------------------------------------- OPCODE PACKSSDW - Pack with Signed Saturation dword to word CPU: all which supported IA MMX: Pentium (P55C only), Pentium (tm) Pro (P6) future models Type of Instruction: User Instruction: PACKSSDW dest,src Description: dest[15..0] <- SaturateSignedDWordToSignedWord dest[31..0] dest[31..16] <- SaturateSignedDWordToSignedWord dest[63..32] dest[47..32] <- SaturateSignedDWordToSignedWord src[31..0] dest[63..46] <- SaturateSignedDWordToSignedWord src[63..32] Note: This instruction packs and saturates signed data from src and dest to dest. If signed value of word larger or smaller that the range of signed byte value is saturated (in case of overflow to 7Fh, in underflow to 80h). Flags affected: None Exceptions: RM PM VM SMM Description #GP(0) If Illegal memory operand's EA in CS,DS,ES,FS,GS #SS(0) If illegal memory operand's EA in SS #PF(fcode) If page fault #AC #AC If unaligned memory reference then alignment check enabled and in ring 3. #UD #UD #UD #UD If CR0.EM = 1 #NM #NM #NM #NM If CR0.TS = 1 #MF #MF #MF #MF If pending FPU Exception ++++++++++++++++++++++++++++++++++++++ COP & Times: PACKSSDW mm,mm/m64 0FH 6BH PostByte P55C: n/a future P6: n/a --------------------------------------------------- OPCODE PACKSSWB - Pack with Signed Saturation word to Byte CPU: all which supported IA MMX: Pentium (P55C only), Pentium (tm) Pro (P6) future models Type of Instruction: User Instruction: PACKSSWB dest,src Description: dest[7..0] <- SaturateSignedWordToSignedByte dest[15..0] dest[15..8] <- SaturateSignedWordToSignedByte dest[31..16] dest[23..16] <- SaturateSignedWordToSignedByte dest[47..32] dest[31..24] <- SaturateSignedWordToSignedByte dest[63..48] dest[39..32] <- SaturateSignedWordToSignedByte src[15..0] dest[47..40] <- SaturateSignedWordToSignedByte src[31..16] dest[55..48] <- SaturateSignedWordToSignedByte src[47..32] dest[63..56] <- SaturateSignedWordToSignedByte src[63..48] Note: This instruction packs and saturates signed data from src and dest to dest Flags affected: None Exceptions: RM PM VM SMM Description #GP(0) If Illegal memory operand's EA in CS,DS,ES,FS,GS #SS(0) If illegal memory operand's EA in SS #PF(fcode) If page fault #AC #AC If unaligned memory reference then alignment check enabled and in ring 3. #UD #UD #UD #UD If CR0.EM = 1 #NM #NM #NM #NM If CR0.TS = 1 #MF #MF #MF #MF If pending FPU Exception ++++++++++++++++++++++++++++++++++++++ COP & Times: PACKSSWB mm,mm/m64 0FH 63H PostByte P55C: n/a future P6: n/a --------------------------------------------------- OPCODE PACKUSWB - Pack with Unsigned Saturation word to Byte CPU: all which supported IA MMX: Pentium (P55C only), Pentium (tm) Pro (P6) future models Type of Instruction: User Instruction: PACKUSWB dest,src Description: dest[7..0] <- SaturateSignedWordToUnSignedByte dest[15..0] dest[15..8] <- SaturateSignedWordToUnSignedByte dest[31..16] dest[23..16] <- SaturateSignedWordToUnSignedByte dest[47..32] dest[31..24] <- SaturateSignedWordToUnSignedByte dest[63..48] dest[39..32] <- SaturateSignedWordToUnSignedByte src[15..0] dest[47..40] <- SaturateSignedWordToUnSignedByte src[31..16] dest[55..48] <- SaturateSignedWordToUnSignedByte src[47..32] dest[63..56] <- SaturateSignedWordToUnSignedByte src[63..48] Note: If signed value of word larger or smaller that the range of unsigned byte, value is saturated (if overflow to FFh, if underflow to 0h). Flags affected: None Exceptions: RM PM VM SMM Description #GP(0) If Illegal memory operand's EA in CS,DS,ES,FS,GS #SS(0) If illegal memory operand's EA in SS #PF(fcode) If page fault #AC #AC If unaligned memory reference then alignment check enabled and in ring 3. #UD #UD #UD #UD If CR0.EM = 1 #NM #NM #NM #NM If CR0.TS = 1 #MF #MF #MF #MF If pending FPU Exception ++++++++++++++++++++++++++++++++++++++ COP & Times: PACKUSWB mm,mm/m64 0FH 67H PostByte P55C: n/a future P6: n/a --------------------------------------------------- OPCODE PADDB - Packed Add Bytes CPU: all which supported IA MMX: Pentium (P55C only), Pentium (tm) Pro (P6) future models Type of Instruction: User Instruction: PADDB dest,src Description: dest[7..0] <- dest[7..0] + src[7..0] dest[15..8] <- dest[15..8] + src[15..8] dest[23..16] <- dest[23..16] + src[23..16] dest[31..24] <- dest[31..24] + src[31..24] dest[39..32] <- dest[39..32] + src[39..32] dest[47..40] <- dest[47..40] + src[47..40] dest[55..48] <- dest[55..48] + src[55..48] dest[63..56] <- dest[63..56] + src[63..56] Note: This instruction adds the bytes of the source to the bytes of the destination and writes the results to the MMX register. When the result is too large to be represented in a packed byte (overflow), the result wraps around and the lower 8 bits are writen to the destination register. Flags affected: None Exceptions: RM PM VM SMM Description #GP(0) If Illegal memory operand's EA in CS,DS,ES,FS,GS #SS(0) If illegal memory operand's EA in SS #PF(fcode) If page fault #AC #AC If unaligned memory reference then alignment check enabled and in ring 3. #UD #UD #UD #UD If CR0.EM = 1 #NM #NM #NM #NM If CR0.TS = 1 #MF #MF #MF #MF If pending FPU Exception #13 #13 If any part of the the operand lies outside of the EA space from 0 to FFFFH ++++++++++++++++++++++++++++++++++++++ COP & Times: PADDB mm,mm/m64 0FH FCH PostByte P55C: n/a future P6: n/a --------------------------------------------------- OPCODE PADDD - Packed Add Dwords CPU: all which supported IA MMX: Pentium (P55C only), Pentium (tm) Pro (P6) future models Type of Instruction: User Instruction: PADDD dest,src Description: dest[31..0] <- dest[31..0] + src[31..0] dest[63..32] <- dest[63..32] + src[63..32] Note: This instruction adds the dwords of the source to the dwords of the destination and writes the results to the MMX register. When the result is too large to be represented in a packed dword (overflow), the result wraps around and the lower 32 bits are writen to the destination register. Flags affected: None Exceptions: RM PM VM SMM Description #GP(0) If Illegal memory operand's EA in CS,DS,ES,FS,GS #SS(0) If illegal memory operand's EA in SS #PF(fcode) If page fault #AC #AC If unaligned memory reference then alignment check enabled and in ring 3. #UD #UD #UD #UD If CR0.EM = 1 #NM #NM #NM #NM If CR0.TS = 1 #MF #MF #MF #MF If pending FPU Exception #13 #13 If any part of the the operand lies outside of the EA space from 0 to FFFFH ++++++++++++++++++++++++++++++++++++++ COP & Times: PADDW mm,mm/m64 0FH FEH PostByte P55C: n/a future P6: n/a --------------------------------------------------- OPCODE PADDSB - Packed Add with Saturation Bytes CPU: all which supported IA MMX: Pentium (P55C only), Pentium (tm) Pro (P6) future models Type of Instruction: User Instruction: PADDSB dest,src Description: dest[7..0] <- SaturateToSignedByte(dest[7..0] + src[7..0]) dest[15..8] <- SaturateToSignedByte(dest[15..8] + src[15..8]) dest[23..16] <- SaturateToSignedByte(dest[23..16] + src[23..16]) dest[31..24] <- SaturateToSignedByte(dest[31..24] + src[31..24]) dest[39..32] <- SaturateToSignedByte(dest[39..32] + src[39..32]) dest[47..40] <- SaturateToSignedByte(dest[47..40] + src[47..40]) dest[55..48] <- SaturateToSignedByte(dest[55..48] + src[55..48]) dest[63..56] <- SaturateToSignedByte(dest[63..56] + src[63..56]) Note: This instruction adds the signed bytes of the source to the bytes of the destination and writes the results to the MMX register. If the result is larger or smaller than the range of a signed byte, the value is saturated (in the case of a overflow - to 7FH, and in the case of an underflow - to 80H). Flags affected: None Exceptions: RM PM VM SMM Description #GP(0) If Illegal memory operand's EA in CS,DS,ES,FS,GS #SS(0) If illegal memory operand's EA in SS #PF(fcode) If page fault #AC #AC If unaligned memory reference then alignment check enabled and in ring 3. #UD #UD #UD #UD If CR0.EM = 1 #NM #NM #NM #NM If CR0.TS = 1 #MF #MF #MF #MF If pending FPU Exception #13 #13 If any part of the the operand lies outside of the EA space from 0 to FFFFH ++++++++++++++++++++++++++++++++++++++ COP & Times: PADDSB mm,mm/m64 0FH ECH PostByte P55C: n/a future P6: n/a ----------------------------------------------- OPCODE PADDSIW - Packed Add with Saturation, using Implied Destination CPU: Cyrix with Extended MMX Instruction Set Type of Instruction: User Instruction: PADDSIW dest, src Description: dest[15..0] <- SaturateToSignedWord(dest[15..0] + src[15..0] dest[31..16] <- SaturateToSignedWord(dest[31..16] + src[31..16] dest[47..32] <- SaturateToSignedWord(dest[47..32] + src[47..32] dest[63..48] <- SaturateToSignedWord(dest[63..48] + src[63..48] Notes: This instruction adds the signed words of the source operand to the signed words of the destination operand and writes the results to the implied MMX register. The purpose of this instruction is the same as the PADDSW instruction, except that it preserves both source operands. The DEST must be an MMX register. The SRC can be either an MMX register or a 64-bit memory operand. The destination is an MMX register which depends on the DEST. Flags Affected: None Exceptions: RM PM VM SMM Description #GP(0) If Illegal memory operands EA in CS,DS,ES,FS,GS #SS(0) If Illegal memory operands EA in SS #PF(fcode) If page fault #AC #AC If unaligned memory reference then alignment check enabled and in ring 3. #UD #UD #UD #UD If CR0.EM = 1 #NM #NM #NM #NM If CR0.TS = 1 #MF #MF #MF #MF If pending FPU Exception #13 #13 If any part of the operand lies outside of the EA space from 0 to FFFFH ++++++++++++++++++++++++++++++++++ COP & Times: PADDSIW mm,mm/m64 0FH 51H PostByte --------------------------------------------------- OPCODE PADDSW - Packed Add with Saturation Words CPU: all which supported IA MMX: Pentium (P55C only), Pentium (tm) Pro (P6) future models Type of Instruction: User Instruction: PADDSW dest,src Description: dest[15..0] <- SaturateToSignedWord(dest[15..0] + src[15..0]) dest[31..16] <- SaturateToSignedWord(dest[31..16] + src[31..16]) dest[47..32] <- SaturateToSignedWord(dest[47..32] + src[47..32]) dest[63..48] <- SaturateToSignedWord(dest[63..48] + src[63..48]) Note: This instruction adds the signed words of the source to the words of the destination and writes the results to the MMX register. If the result is larger or smaller than the range of a signed word, the value is saturated (in the case of a overflow - to 7FFFH, and in the case of an underflow - to 8000H). Flags affected: None Exceptions: RM PM VM SMM Description #GP(0) If Illegal memory operand's EA in CS,DS,ES,FS,GS #SS(0) If illegal memory operand's EA in SS #PF(fcode) If page fault #AC #AC If unaligned memory reference then alignment check enabled and in ring 3. #UD #UD #UD #UD If CR0.EM = 1 #NM #NM #NM #NM If CR0.TS = 1 #MF #MF #MF #MF If pending FPU Exception #13 #13 If any part of the the operand lies outside of the EA space from 0 to FFFFH ++++++++++++++++++++++++++++++++++++++ COP & Times: PADDSW mm,mm/m64 0FH EDH PostByte P55C: n/a future P6: n/a --------------------------------------------------- OPCODE PADDUSB - Packed Add Unsigned with Saturation Bytes CPU: all which supported IA MMX: Pentium (P55C only), Pentium (tm) Pro (P6) future models Type of Instruction: User Instruction: PADDUSB dest,src Description: dest[7..0] <- SaturateToUnsignedByte(dest[7..0] + src[7..0]) dest[15..8] <- SaturateToUnsignedByte(dest[15..8] + src[15..8]) dest[23..16] <- SaturateToUnsignedByte(dest[23..16] + src[23..16]) dest[31..24] <- SaturateToUnsignedByte(dest[31..24] + src[31..24]) dest[39..32] <- SaturateToUnsignedByte(dest[39..32] + src[39..32]) dest[47..40] <- SaturateToUnsignedByte(dest[47..40] + src[47..40]) dest[55..48] <- SaturateToUnsignedByte(dest[55..48] + src[55..48]) dest[63..56] <- SaturateToUnsignedByte(dest[63..56] + src[63..56]) Note: This instruction adds the unsigned bytes of the source to the unsigned bytes of the destination operand and writes the results to the MMX register. When the result is larger than the range of an unsigned byte (overflow), the value is saturated to FFH. When the result is smaller than the range of an unsigned byte (underflow), the value is saturated to 00H. Flags affected: None Exceptions: RM PM VM SMM Description #GP(0) If Illegal memory operand's EA in CS,DS,ES,FS,GS #SS(0) If illegal memory operand's EA in SS #PF(fcode) If page fault #AC #AC If unaligned memory reference then alignment check enabled and in ring 3. #UD #UD #UD #UD If CR0.EM = 1 #NM #NM #NM #NM If CR0.TS = 1 #MF #MF #MF #MF If pending FPU Exception #13 #13 If any part of the the operand lies outside of the EA space from 0 to FFFFH ++++++++++++++++++++++++++++++++++++++ COP & Times: PADDUSB mm,mm/m64 0FH DCH PostByte P55C: n/a future P6: n/a --------------------------------------------------- OPCODE PADDUSW - Packed Add Unsigned with Saturation Words CPU: all which supported IA MMX: Pentium (P55C only), Pentium (tm) Pro (P6) future models Type of Instruction: User Instruction: PADDUSW dest,src Description: dest[15..0] <- SaturateToUnsignedWord(dest[15..0] + src[15..0]) dest[31..16] <- SaturateToUnsignedWord(dest[31..16] + src[31..16]) dest[47..32] <- SaturateToUnsignedWord(dest[47..32] + src[47..32]) dest[63..48] <- SaturateToUnsignedWord(dest[63..48] + src[63..48]) Note: This instruction adds the unsigned words of the source to the unsigned words of the destination operand and writes the results to the MMX register. When the result is larger than the range of an unsigned word (overflow), the value is saturated to FFFFH. When the result is smaller than the range of an unsigned byte (underflow), the value is saturated to 0000H. Flags affected: None Exceptions: RM PM VM SMM Description #GP(0) If Illegal memory operand's EA in CS,DS,ES,FS,GS #SS(0) If illegal memory operand's EA in SS #PF(fcode) If page fault #AC #AC If unaligned memory reference then alignment check enabled and in ring 3. #UD #UD #UD #UD If CR0.EM = 1 #NM #NM #NM #NM If CR0.TS = 1 #MF #MF #MF #MF If pending FPU Exception #13 #13 If any part of the the operand lies outside of the EA space from 0 to FFFFH ++++++++++++++++++++++++++++++++++++++ COP & Times: PADDUSW mm,mm/m64 0FH DDH PostByte P55C: n/a future P6: n/a --------------------------------------------------- OPCODE PADDW - Packed Add Words CPU: all which supported IA MMX: Pentium (P55C only), Pentium (tm) Pro (P6) future models Type of Instruction: User Instruction: PADDW dest,src Description: dest[15..0] <- dest[15..0] + src[15..0] dest[31..16] <- dest[31..16] + src[31..16] dest[47..32] <- dest[47..32] + src[47..32] dest[63..48] <- dest[63..48] + src[63..48] Note: This instruction adds the words of the source to the words of the destination and writes the results to the MMX register. When the result is too large to be represented in a packed word (overflow), the result wraps around and the lower 16 bits are writen to the destination register. Flags affected: None Exceptions: RM PM VM SMM Description #GP(0) If Illegal memory operand's EA in CS,DS,ES,FS,GS #SS(0) If illegal memory operand's EA in SS #PF(fcode) If page fault #AC #AC If unaligned memory reference then alignment check enabled and in ring 3. #UD #UD #UD #UD If CR0.EM = 1 #NM #NM #NM #NM If CR0.TS = 1 #MF #MF #MF #MF If pending FPU Exception #13 #13 If any part of the the operand lies outside of the EA space from 0 to FFFFH ++++++++++++++++++++++++++++++++++++++ COP & Times: PADDW mm,mm/m64 0FH FDH PostByte P55C: n/a future P6: n/a --------------------------------------------------- OPCODE PAND - Bitwise Logical And CPU: all which supported IA MMX: Pentium (P55C only), Pentium (tm) Pro (P6) future models Type of Instruction: User Instruction: PAND dest,src Description: dest <- dest AND src Note: AND 64 bits from MMXregister/memory to MMX register. Flags affected: None Exceptions: RM PM VM SMM Description #GP(0) If Illegal memory operand's EA in CS,DS,ES,FS,GS #SS(0) If illegal memory operand's EA in SS #PF(fcode) If page fault #AC #AC If unaligned memory reference then alignment check enabled and in ring 3. #UD #UD #UD #UD If CR0.EM = 1 #NM #NM #NM #NM If CR0.TS = 1 #MF #MF #MF #MF If pending FPU Exception #13 #13 If any part of the the operand lies outside of the EA space from 0 to FFFFH ++++++++++++++++++++++++++++++++++++++ COP & Times: PAND mm,mm/m64 0FH DBH PostByte P55C: n/a future P6: n/a --------------------------------------------------- OPCODE PANDN - Bitwise Logical And Not CPU: all which supported IA MMX: Pentium (P55C only), Pentium (tm) Pro (P6) future models Type of Instruction: User Instruction: PANDN dest,src Description: dest <- (NOT dest) AND src Note: Invert the 64 bits in MMX register, AND inverted MMX register with MMXregister/memory. Flags affected: None Exceptions: RM PM VM SMM Description #GP(0) If Illegal memory operand's EA in CS,DS,ES,FS,GS #SS(0) If illegal memory operand's EA in SS #PF(fcode) If page fault #AC #AC If unaligned memory reference then alignment check enabled and in ring 3. #UD #UD #UD #UD If CR0.EM = 1 #NM #NM #NM #NM If CR0.TS = 1 #MF #MF #MF #MF If pending FPU Exception #13 #13 If any part of the the operand lies outside of the EA space from 0 to FFFFH ++++++++++++++++++++++++++++++++++++++ COP & Times: PANDN mm,mm/m64 0FH DFH PostByte P55C: n/a future P6: n/a ----------------------------------------------- OPCODE PAVEB - Packed Average CPU: Cyrix with Extended MMX Instruction Set Type of Instruction: User Instruction: PAVEB dest, src Description: dest[7..0] <- (dest[7..0] + src[7..0]) >> 1 dest[15..8] <- (dest[15..8] + src[15..8]) >> 1 dest[23..16] <- (dest[23..16] + src[23..16]) >> 1 dest[31..24] <- (dest[31..24] + src[31..24]) >> 1 dest[39..32] <- (dest[39..32] + src[39..32]) >> 1 dest[47..40] <- (dest[47..40] + src[47..40]) >> 1 dest[55..48] <- (dest[55..48] + src[55..48]) >> 1 dest[63..56] <- (dest[63..56] + src[63..56]) >> 1 Notes: The PAVEB insruction calculates the average of the unsigned bytes of the source operand and the unsigned bytes of the destination operand and writes the result to the MMX register. The PAVEB instruction cannot overflow. M2 hardware versions before v1.3 interpret values as signed bytes on this instruction. Flags Affected: None Exceptions: RM PM VM SMM Description #GP(0) If Illegal memory operands EA in CS,DS,ES,FS,GS #SS(0) If Illegal memory operands EA in SS #PF(fcode) If page fault #AC #AC If unaligned memory reference then alignment check enabled and in ring 3. #UD #UD #UD #UD If CR0.EM = 1 #NM #NM #NM #NM If CR0.TS = 1 #MF #MF #MF #MF If pending FPU Exception #13 #13 If any part of the operand lies outside of the EA space from 0 to FFFFH ++++++++++++++++++++++++++++++++++ COP & Times: PAVEB mm,mm/m64 0FH 50H PostByte ----------------------------------------------------------------- PAVGB - Packed Average Byte CPU: Pentium III+ (KNI/MMX2), AMD Athlon (AMD EMMX) Type of instruction: User Instruction: PAVGB dest,src Description: define AVERAGE(bits) // This is Unsigned operation :)) dest[bits] <- (size(8bits,(src[bits] + dest[bits])) + 1) >> 1; enddef AVERAGE(7..0); AVERAGE(15..8); AVERAGE(23..16); AVERAGE(31..24); AVERAGE(39..32); AVERAGE(47..40); AVERAGE(55..48); AVERAGE(63..56); Physical Form and Timing: PAVGB mm1,mm2/m64 ---- 0F E0 /r ---- ?? ----------------------------------------------- OPCODE PAVGUSB - Avarage of Unsigned packed 8-bit Values CPU: AMD-3D Type of Instruction: User Instruction: PAVGUSB dest,src Description: dest[7..0] <- (dest[7..0] + src[7..0]) / 2; dest[15..8] <- (dest[15..8] + src[15..8]) / 2; dest[23..16] <- (dest[23..16] + src[23..16]) / 2; dest[31..24] <- (dest[31..24] + src[31..24]) / 2; dest[39..32] <- (dest[39..32] + src[39..32]) / 2; dest[47..40] <- (dest[47..40] + src[47..40]) / 2; dest[55..48] <- (dest[55..48] + src[55..48]) / 2; dest[63..56] <- (dest[63..56] + src[63..56]) / 2; Note: so, saturation rounding: (FFH + FFH) / 2 => FFh Flags Affected: None ++++++++++++++++++++++++++++++++++ COP & Times: PAVGUSB mm,mm/m64 0FH 0FH BFH Postbyte ----------------------------------------------------------------- PAVGW - Packed Average Word CPU: Pentium III+ (KNI/MMX2), AMD Athlon (AMD EMMX) Type of instruction: User Instruction: PAVGW dest,src Description: define AVERAGE(bits) // This is Unsigned operation dest[bits] <- (size(16bits,(src[bits] + dest[bits])) + 1) >> 1; enddef AVERAGE(15..0); AVERAGE(31..16); AVERAGE(47..32); AVERAGE(63..48); Physical Form and Timing: PAVGW mm1,mm2/m64 ---- 0F E3 /r ---- ?? --------------------------------------------------- OPCODE PCMPEQB - Packed Compare for Equal Bytes CPU: all which supported IA MMX: Pentium (P55C only), Pentium (tm) Pro (P6) future models Type of Instruction: User Instruction: PCMPEQB dest,src Description: IF dest[7..0] = src[7..0] THEN dest[7..0] <- FFH ELSE dest[7..0] <- 00H IF dest[15..8] = src[15..8] THEN dest[15..8] <- FFH ELSE dest[15..8] <- 00H IF dest[23..16] = src[23..16] THEN dest[23..16] <- FFH ELSE dest[23..16] <- 00H IF dest[31..24] = src[31..24] THEN dest[31..24] <- FFH ELSE dest[31..24] <- 00H IF dest[39..32] = src[39..32] THEN dest[39..32] <- FFH ELSE dest[39..32] <- 00H IF dest[47..40] = src[47..40] THEN dest[47..40] <- FFH ELSE dest[47..40] <- 00H IF dest[55..48] = src[55..48] THEN dest[55..48] <- FFH ELSE dest[55..48] <- 00H IF dest[63..56] = src[63..56] THEN dest[63..56] <- FFH ELSE dest[63..56] <- 00H Note: Compare packed byte in MMXregister/memory with packed byte in MMX register for equality. Flags affected: None Exceptions: RM PM VM SMM Description #GP(0) If Illegal memory operand's EA in CS,DS,ES,FS,GS #SS(0) If illegal memory operand's EA in SS #PF(fcode) If page fault #AC #AC If unaligned memory reference then alignment check enabled and in ring 3. #UD #UD #UD #UD If CR0.EM = 1 #NM #NM #NM #NM If CR0.TS = 1 #MF #MF #MF #MF If pending FPU Exception #13 #13 If any part of the the operand lies outside of the EA space from 0 to FFFFH ++++++++++++++++++++++++++++++++++++++ COP & Times: PCMPEQB mm,mm/m64 0FH 74H PostByte P55C: n/a future P6: n/a --------------------------------------------------- OPCODE PCMPEQD - Packed Compare for Equal Dwords CPU: all which supported IA MMX: Pentium (P55C only), Pentium (tm) Pro (P6) future models Type of Instruction: User Instruction: PCMPEQD dest,src Description: IF dest[31..0] = src[31..0] THEN dest[31..0] <- FFFFFFFFH ELSE dest[31..0] <- 00000000H IF dest[63..32] = src[63..32] THEN dest[63..32] <- FFFFFFFFH ELSE dest[63..32] <- 00000000H Note: Compare packed dword in MMXregister/memory with packed dword in MMX register for equality. Flags affected: None Exceptions: RM PM VM SMM Description #GP(0) If Illegal memory operand's EA in CS,DS,ES,FS,GS #SS(0) If illegal memory operand's EA in SS #PF(fcode) If page fault #AC #AC If unaligned memory reference then alignment check enabled and in ring 3. #UD #UD #UD #UD If CR0.EM = 1 #NM #NM #NM #NM If CR0.TS = 1 #MF #MF #MF #MF If pending FPU Exception #13 #13 If any part of the the operand lies outside of the EA space from 0 to FFFFH ++++++++++++++++++++++++++++++++++++++ COP & Times: PCMPEQW mm,mm/m64 07H 76H PostByte P55C: n/a future P6: n/a --------------------------------------------------- OPCODE PCMPEQW - Packed Compare for Equal Words CPU: all which supported IA MMX: Pentium (P55C only), Pentium (tm) Pro (P6) future models Type of Instruction: User Instruction: PCMPEQW dest,src Description: IF dest[15..0] = src[15..0] THEN dest[15..0] <- FFFFH ELSE dest[15..0] <- 0000H IF dest[31..16] = src[31..16] THEN dest[31..16] <- FFFFH ELSE dest[31..16] <- 0000H IF dest[47..32] = src[47..32] THEN dest[47..32] <- FFFFH ELSE dest[47..32] <- 0000H IF dest[63..48] = src[63..48] THEN dest[63..48] <- FFFFH ELSE dest[63..48] <- 0000H Note: Compare packed word in MMXregister/memory with packed word in MMX register for equality. Flags affected: None Exceptions: RM PM VM SMM Description #GP(0) If Illegal memory operand's EA in CS,DS,ES,FS,GS #SS(0) If illegal memory operand's EA in SS #PF(fcode) If page fault #AC #AC If unaligned memory reference then alignment check enabled and in ring 3. #UD #UD #UD #UD If CR0.EM = 1 #NM #NM #NM #NM If CR0.TS = 1 #MF #MF #MF #MF If pending FPU Exception #13 #13 If any part of the the operand lies outside of the EA space from 0 to FFFFH ++++++++++++++++++++++++++++++++++++++ COP & Times: PCMPEQW mm,mm/m64 07H 75H PostByte P55C: n/a future P6: n/a --------------------------------------------------- OPCODE PCMPGTB - Packed Compare for Greater Than Bytes CPU: all which supported IA MMX: Pentium (P55C only), Pentium (tm) Pro (P6) future models Type of Instruction: User Instruction: PCMPGTB dest,src Description: IF dest[7..0] > src[7..0] THEN dest[7..0] <- FFH ELSE dest[7..0] <- 00H IF dest[15..8] > src[15..8] THEN dest[15..8] <- FFH ELSE dest[15..8] <- 00H IF dest[23..16] > src[23..16] THEN dest[23..16] <- FFH ELSE dest[23..16] <- 00H IF dest[31..24] > src[31..24] THEN dest[31..24] <- FFH ELSE dest[31..24] <- 00H IF dest[39..32] > src[39..32] THEN dest[39..32] <- FFH ELSE dest[39..32] <- 00H IF dest[47..40] > src[47..40] THEN dest[47..40] <- FFH ELSE dest[47..40] <- 00H IF dest[55..48] > src[55..48] THEN dest[55..48] <- FFH ELSE dest[55..48] <- 00H IF dest[63..56] > src[63..56] THEN dest[63..56] <- FFH ELSE dest[63..56] <- 00H Note: Compare packed byte in MMX register with packed byte in MMXregister/ /memory for greater value. Flags affected: None Exceptions: RM PM VM SMM Description #GP(0) If Illegal memory operand's EA in CS,DS,ES,FS,GS #SS(0) If illegal memory operand's EA in SS #PF(fcode) If page fault #AC #AC If unaligned memory reference then alignment check enabled and in ring 3. #UD #UD #UD #UD If CR0.EM = 1 #NM #NM #NM #NM If CR0.TS = 1 #MF #MF #MF #MF If pending FPU Exception #13 #13 If any part of the the operand lies outside of the EA space from 0 to FFFFH ++++++++++++++++++++++++++++++++++++++ COP & Times: PCMPGTB mm,mm/m64 0FH 64H PostByte P55C: n/a future P6: n/a --------------------------------------------------- OPCODE PCMPGTD - Packed Compare for Greater Than Dwords CPU: all which supported IA MMX: Pentium (P55C only), Pentium (tm) Pro (P6) future models Type of Instruction: User Instruction: PCMPGTD dest,src Description: IF dest[31..0] > src[31..0] THEN dest[31..0] <- FFFFFFFFH ELSE dest[31..0] <- 00000000H IF dest[63..32] > src[63..32] THEN dest[63..32] <- FFFFFFFFH ELSE dest[63..32] <- 00000000H Note: Compare packed dword in MMX register with packed dword in MMXregister/ /memory for greater value. Flags affected: None Exceptions: RM PM VM SMM Description #GP(0) If Illegal memory operand's EA in CS,DS,ES,FS,GS #SS(0) If illegal memory operand's EA in SS #PF(fcode) If page fault #AC #AC If unaligned memory reference then alignment check enabled and in ring 3. #UD #UD #UD #UD If CR0.EM = 1 #NM #NM #NM #NM If CR0.TS = 1 #MF #MF #MF #MF If pending FPU Exception #13 #13 If any part of the the operand lies outside of the EA space from 0 to FFFFH ++++++++++++++++++++++++++++++++++++++ COP & Times: PCMPGTW mm,mm/m64 0FH 66H PostByte P55C: n/a future P6: n/a --------------------------------------------------- OPCODE PCMPGTW - Packed Compare for Greater Than Words CPU: all which supported IA MMX: Pentium (P55C only), Pentium (tm) Pro (P6) future models Type of Instruction: User Instruction: PCMPGTW dest,src Description: IF dest[15..0] > src[15..0] THEN dest[15..0] <- FFFFH ELSE dest[15..0] <- 0000H IF dest[31..16] > src[31..16] THEN dest[31..16] <- FFFFH ELSE dest[31..16] <- 0000H IF dest[47..32] > src[47..32] THEN dest[47..32] <- FFFFH ELSE dest[47..32] <- 0000H IF dest[63..48] > src[63..48] THEN dest[63..48] <- FFFFH ELSE dest[63..48] <- 0000H Note: Compare packed word in MMX register with packed word in MMXregister/ memory for greater value. Flags affected: None Exceptions: RM PM VM SMM Description #GP(0) If Illegal memory operand's EA in CS,DS,ES,FS,GS #SS(0) If illegal memory operand's EA in SS #PF(fcode) If page fault #AC #AC If unaligned memory reference then alignment check enabled and in ring 3. #UD #UD #UD #UD If CR0.EM = 1 #NM #NM #NM #NM If CR0.TS = 1 #MF #MF #MF #MF If pending FPU Exception #13 #13 If any part of the the operand lies outside of the EA space from 0 to FFFFH ++++++++++++++++++++++++++++++++++++++ COP & Times: PCMPGTW mm,mm/m64 0FH 65H PostByte P55C: n/a future P6: n/a ----------------------------------------------- OPCODE PDISTIB - Packed Distance and Accumulate with Implied Register CPU: Cyrix with Extended MMX Instruction Set Type of Instruction: User Instruction: PDISTIB dest, src Description: dest[7..0] <- SaturateToUnsignedByte(dest[7..0] + abs(dest[7..0] - src[7..0])) dest[15..8] <- SaturateToUnsignedByte(dest[15..8] + abs(dest[15..8] - src[15..8])) dest[23..16] <- SaturateToUnsignedByte(dest[23..16] + abs(dest[23..16] - src[23..16])) dest[31..24] <- SaturateToUnsignedByte(dest[31..24] + abs(dest[31..24] - src[31..24])) dest[39..32] <- SaturateToUnsignedByte(dest[39..32] + abs(dest[39..32] - src[39..32])) dest[47..40] <- SaturateToUnsignedByte(dest[47..40] + abs(dest[47..40] - src[47..40])) dest[55..48] <- SaturateToUnsignedByte(dest[55..48] + abs(dest[55..48] - src[55..48])) dest[63..56] <- SaturateToUnsignedByte(dest[63..56] + abs(dest[63..56] - src[63..56])) Notes: The PDISTIB instruction calculates the distance between the unsigned bytes of two source operands, adds the result to the unsigned byte in the implied destination operand, and saturates the result. The result is written to the implied MMX register. The DEST must be an MMX register. The SRC must be a 64-bit memory operand. The accumulator and destination is an MMX register which depends on the DEST. Flags Affected: None Exceptions: RM PM VM SMM Description #GP(0) If Illegal memory operands EA in CS,DS,ES,FS,GS #SS(0) If Illegal memory operands EA in SS #PF(fcode) If page fault #AC #AC If unaligned memory reference then alignment check enabled and in ring 3. #UD #UD #UD #UD If CR0.EM = 1 #NM #NM #NM #NM If CR0.TS = 1 #MF #MF #MF #MF If pending FPU Exception #13 #13 If any part of the operand lies outside of the EA space from 0 to FFFFH ++++++++++++++++++++++++++++++++++ COP & Times: PDISTIB mm,m64 0FH 54H PostByte ----------------------------------------------------------------- PEXTRW - Extract Word CPU: Pentium III+ (KNI/MMX2), AMD Athlon (AMD EMMX) Type of instruction: User Instruction: PEXTRW dest,src,which_word Description: word TMP = which_word AND 0x3; word MM_TMP = (src >> (TMP * 16)) AND 0xffff; dest[15..0] <- MM_TMP; dest[31..16] <- 0; Physical Form and Timing: PEXTRW r32,mm,imm8 ---- 0F C5 /r imm8 ---- ?? ----------------------------------------------- OPCODE PF2ID - Convert Packed F.P. to 32-bit Integer CPU: AMD-3D Type of Instruction: User Instruction: PF2ID dest,src Description: if (src[31..0] > 2^31) then dest[31..0] <- 7FFFFFFFh; if (src[31..0] <= -2^31) then dest[31..0] <- 80000000h; dest[31..0] <- truncate(src[31..0]); if (src[63..32] > 2^31) then dest[63..32] <- 7FFFFFFFh; if (src[63..32] <= -2^31) then dest[63..32] <- 80000000h; dest[63..32] <- truncate(src[63..32]); Flags Affected: None ++++++++++++++++++++++++++++++++++ COP & Times: PF2ID mm,mm/m64 0FH 0FH 1DH Postbyte ----------------------------------------------- OPCODE PF2IW - Packed FP to Integer Word conversion with sign extend CPU: 3DNow! extension (Athlon CPU) Type of Instruction: User Instruction: PF2IW dest,src Description: if (src[31:0] >= 2^15) dest[31:0] = 00007fffh; elseif (src[31:0] <= -2^15) dest[31:0] = ffff8000h; else dest[31:0] <- int(src[31:0]); if (src[63:32] >= 2^15) dest[63:32] = 00007fffh; elseif (src[63:32] <= -2^15) dest[63:32] = ffff8000h; else dest[63:32] <- int(src[63:32]); Note: Flags Affected: None ++++++++++++++++++++++++++++++++++ COP & Times: PF2IW mm,mm/m64 0F 0F 1C Postbyte ----------------------------------------------- OPCODE PFACC - F.P. Accumulate CPU: AMD-3D Type of Instruction: User Instruction: PFACC dest,src Description: dest[31..0] <- dest[31..0] + dest[63..32]; dest[63..32] <- src[31..0] + src [63..32]; Flags Affected: None ++++++++++++++++++++++++++++++++++ COP & Times: PFACC mm,mm/m64 0FH 0FH AEH Postbyte ----------------------------------------------- OPCODE PFADD - Packed F.P. Addition CPU: AMD-3D Type of Instruction: User Instruction: PFADD dest,src Description: dest[31..0] <- dest[31..0] + src[31..0]; dest[63..32] <- dest[63..32] + src[63..32]; Flags Affected: None ++++++++++++++++++++++++++++++++++ COP & Times: PFADD mm,mm/m64 0FH 0FH 9EH Postbyte ----------------------------------------------- OPCODE PFCMPEQ - Packed F.P. comparson, equal to CPU: AMD-3D Type of Instruction: User Instruction: PFCMPEQ dest,src Description: if dest[31..0] == src[31..0] then dest[31..0] <- FFFFFFFFh else dest[31..0] <- 00000000h if dest[63..32] == src[63..32] then dest[63..32] <- FFFFFFFFh else dest[63..32] <- 00000000h Flags Affected: None ++++++++++++++++++++++++++++++++++ COP & Times: PFCMPEQ mm,mm/m64 0FH 0FH B0H Postbyte ----------------------------------------------- OPCODE PFCMPGE - Packed F.P. comparison, greater or equal to CPU: AMD-3D Type of Instruction: User Instruction: PFCMPGE dest,src Description: if dest[31..0] >= src[31..0] then dest[31..0] <- FFFFFFFFh else dest[31..0] <- 00000000h if dest[63..32] >= src[63..32] then dest[63..32] <- FFFFFFFFh else dest[63..32] <- 00000000h Flags Affected: None ++++++++++++++++++++++++++++++++++ COP & Times: PFCMPGE mm,mm/m64 0FH 0FH 90H Postbyte ----------------------------------------------- OPCODE PFCMPGT - Packed F.P. compariason, greater to CPU: AMD-3D Type of Instruction: User Instruction: PFCMPGT dest,src Description: if dest[31..0] > src[31..0] then dest[31..0] <- FFFFFFFFh else dest[31..0] <- 00000000h if dest[63..32] > src[63..32] then dest[63..32] <- FFFFFFFFh else dest[63..32] <- 00000000h Flags Affected: None ++++++++++++++++++++++++++++++++++ COP & Times: PFCMPGT mm,mm/m64 0FH 0FH A0H Postbyte ----------------------------------------------- OPCODE PFMAX - Packed F.P. Maximum CPU: AMD-3D Type of Instruction: User Instruction: PFMAX dest,src Description: if src[31..0] > dest[31..0] then dest[31..0] <- src[31..0]; if src[63..32] > dest[63..32] then dest[63..32] <- src[63..32]; Note: Flags Affected: None ++++++++++++++++++++++++++++++++++ COP & Times: PFMAX mm,mm/m64 0FH 0FH A4H ----------------------------------------------- OPCODE PFMIN - Packed F.P. Minimum CPU: AMD-3D Type of Instruction: User Instruction: PFMIN dest,src Description: if src[31..0] < dest[31..0] then dest[31..0] <- src[31..0]; if src[63..32] < dest[63..32] then dest[63..32] <- src[63..32]; Note: Flags Affected: None ++++++++++++++++++++++++++++++++++ COP & Times: PFMIN mm,mm/m64 0FH 0FH 94H ----------------------------------------------- OPCODE PFMUL - Packed F.P. Multiplication CPU: AMD-3D Type of Instruction: User Instruction: PFMUL dest,src Description: dest[31..0] <- dest[31..0] * src[31..0]; dest[63..32] <- dest[63..32] * src[63..32]; Flags Affected: None ++++++++++++++++++++++++++++++++++ COP & Times: PFMUL mm,mm/m64 0FH 0FH B4H Postbyte ----------------------------------------------- OPCODE PFNACC - Packed Floating Point negative accumulate CPU: 3DNow! extension (Athlon CPU) Type of Instruction: User Instruction: PFNACC dest,src Description: dest[31:0] <- dest[31:0] - dest[63:32]; dest[63:32] <- src[31:0] - src[63:32] Note: Flags Affected: None ++++++++++++++++++++++++++++++++++ COP & Times: PFNACC mm,mm/m64 0F 0F 8A Postbyte ----------------------------------------------- OPCODE PFPNACC - Packed Floating Point Mixed Positive-Negative Accumulate CPU: 3DNow! extension (Athlon CPU) Type of Instruction: User Instruction: PFPNACC dest,src Description: dest[31:0] <- dest[31:0] - dest[63:32]; dest[63:32] <- src[31:0] + src[63:32]; Note: Flags Affected: None ++++++++++++++++++++++++++++++++++ COP & Times: PFPNACC mm,mm/m64 0F 0F 8E Postbyte ----------------------------------------------- OPCODE PFRCP - F.P. Reciprocal Approximation CPU: AMD-3D Type of Instruction: User Instruction: PFRCP dest,src Description: dest[31..0] <- Reciprocal(src[31..0]); dest[63..32] <- Reciprocal(src[63..32]); Note: Newton-Raphson algorithm: Division ---------- q = a/b; X(i+1) = X(i) * (2 - b * X(i)); X0 = RFRCP(b); X1 = RFRCPIT1(b,X0); X2 = RFRCPIT2(X1,X0); q = PFMUL(a,X2); Square Root -------------- X(i+1) = 1/2 * X(i) * (3 - b * X(i)^2); X0 = PFRSQRT(b); X1 = PFMUL(X0,X0); X2 = PFRSQIT(b,X1); X3 = PFRCPIT2(X2,X0); X4 = PFMUL(b,X3); Flags Affected: None ++++++++++++++++++++++++++++++++++ COP & Times: PFRCP mm,mm/m64 0FH 0FH 96H Postbyte ----------------------------------------------- OPCODE PFRCPIT1 - Packed F.P. Reciprocal, first iteration Step CPU: AMD-3D Type of Instruction: User Instruction: PFRCIT1 dest,src Description: dest[31..0] <- First_Step_Reciprocal(src[31..0]); dest[63..32] <- First_Step_Reciprocal(src[63..32]); Note: see PFRCP for more info. Flags Affected: None ++++++++++++++++++++++++++++++++++ COP & Times: PFRCIT1 mm,mm/m64 0FH 0FH A6H Postbyte ----------------------------------------------- OPCODE PFRCPIT2 - Packed F.P. Reciprocal, second iteration Step CPU: AMD-3D Type of Instruction: User Instruction: PFRCIT2 dest,src Description: dest[31..0] <- Second_Step_Reciprocal(src[31..0]); dest[63..32] <- Second_Step_Reciprocal(src[63..32]); Note: see PFRCP for more info. Flags Affected: None ++++++++++++++++++++++++++++++++++ COP & Times: PFRCIT2 mm,mm/m64 0FH 0FH B6H Postbyte ----------------------------------------------- OPCODE PFRSQIT1 - Packed F.P. Reciprocal Square Root, 1st iteration step CPU: AMD-3D Type of Instruction: User Instruction: PFRSQIT1 dest,src Description: dest[31..0] <- First_Step_Reciprocal_Square_Root(src[31..0]); dest[63..32] <- First_Step_Reciprocal_Square_Root(src[63..32]); Note: see RFRCP for more info Flags Affected: None ++++++++++++++++++++++++++++++++++ COP & Times: PFRSQIT1 mm,mm/m64 0FH 0FH A7H Postbyte ----------------------------------------------- OPCODE PFRSQRT - F.P. Reciprocal Square Root Approximation CPU: AMD-3D Type of Instruction: User Instruction: PFRSQRT dest,src Description: dest[31..0] <- Reciprocal_Square_Root(src[31..0]); dest[63..32] <- Reciprocal_Square_Root(src[63..32]); Note: see RFRCP for more info Flags Affected: None ++++++++++++++++++++++++++++++++++ COP & Times: PFRSQRT mm,mm/m64 0FH 0FH 97H Postbyte ----------------------------------------------- OPCODE PFSUB - Packed F.P. Subtraction CPU: AMD-3D Type of Instruction: User Instruction: PFSUB dest,src Description: dest[31..0] <- dest[31..0] - src[31..0]; dest[63..32] <- dest[63..32] - src[63..32]; Flags Affected: None ++++++++++++++++++++++++++++++++++ COP & Times: PFSUB mm,mm/m64 0FH 0FH 9AH Postbyte ----------------------------------------------- OPCODE PFSUBR - Packed F.P. Reverse Subtraction CPU: AMD-3D Type of Instruction: User Instruction: PFSUBR dest,src Description: dest[31..0] <- src[31..0] - dest[31..0]; dest[63..32] <- src[63..32] - dest[63..32]; Flags Affected: None ++++++++++++++++++++++++++++++++++ COP & Times: PFSUBR mm,mm/m64 0FH 0FH AAH Postbyte ----------------------------------------------- OPCODE PI2FD - Packed 32-bit Integer to F.P. conversion CPU: AMD-3D Type of Instruction: User Instruction: PI2FD dest,src Description: dest[31..0] <- float(src[31..0]); dest[63..32] <- float(src[63..32]); Flags Affected: None ++++++++++++++++++++++++++++++++++ COP & Times: PI2FD mm,mm/m64 0FH 0FH 0DH Postbyte ----------------------------------------------- OPCODE PI2FW - Packed 16-bit Integer to FP Conversion CPU: 3DNow! extension (Athlon CPU) Type of Instruction: User Instruction: PI2FW dest,src Description: dest[31:0] <- float(src[15:0]); dest[63:32] <- float(src[47:32]); Note: Flags Affected: None ++++++++++++++++++++++++++++++++++ COP & Times: PI2FW mm,mm/m64 0F 0F 0C Postbyte ----------------------------------------------------------------- PINSRW - Insert Word CPU: Pentium III+ (KNI/MMX2), AMD Athlon (AMD EMMX) Type of instruction: User Instruction: PINSRW dest,src,which_word Description: word TMP = which_word AND 0x3; switch (TMP) case 0: word MASK = 0x000000000000FFFF case 1: word MASK = 0x00000000FFFF0000 case 2: word MASK = 0x0000FFFF00000000 case 4: word MASK = 0xFFFF000000000000 endswitch dest <- (dest and NOT(MASK)) OR ((src << (TMP * 16)) AND MASK); Physical Form and Timing: PINSRW mm,r32/m16,imm8 ---- 0F C4 /r imm8 ---- ?? ----------------------------------------------- OPCODE PMACHRIW - Packed Multiply and Accumulate with Rounding CPU: Cyrix with Extended MMX Instruction Set Type of Instruction: User Instruction: PMACHRIW dest, src Description: dest[15..0] <- dest[15..0] + (dest[15..0]*src[15..0] + 00004000H)[30..15] dest[31..16] <- dest[31..16] + (dest[31..16]*src[31..16] + 00004000H)[30..15] dest[47..32] <- dest[47..32] + (dest[47..32]*src[47..32] + 00004000H)[30..15] dest[63..48] <- dest[63..48] + (dest[63..48]*src[63..48] + 00004000H)[30..15] Notes: The PMACHRIW multiplies the two source operands using the method described for PMULHRW, and then accumulates the result with the value in the implied destination register using wrap-around arithmetic. The final result is placed in the implied DEST register. The DEST must be an MMX register. The SRC must be a 64-bit memory operand. The destination operand is an implied MMX register that depend